Menta Sas

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Menta delivers standard-cell based, embedded FPGA IPs in RTL and GDS2 format, for SoC, ASIC or ASSP designs. Our technology lets you effortlessly update your silicon post-production, whether to fix a bug, implement customer-specific features, adapt to evolving standards, or enhance security. Menta IPs are delivered with standard EDA tools, and support process technologies and nodes from any vendor (TSMC, GF... from 350nm all the way down to 3nm).

Company Details

Employees
61
Founded
-
Address
2405, Route Des Dolines, Valbonne / Sophia-Antipolis,provence-Alpes-Cote D'azur 06560,france
Phone
(650) 208-6548
Email
in****@****ina.com
Industry
Semiconductor Manufacturing
NAICS
Semiconductor and Other Electronic Component Manufacturing
HQ
Valbonne / Sophia-Antipolis, Provence-Alpes-Cote d'Azur
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News

Nine Compelling Reasons Why Menta eFPGA Is Essential for Achieving True Crypto Agility in Your ASIC or SoC - EE Times

Nine Compelling Reasons Why Menta eFPGA Is Essential for Achieving True Crypto Agility in Your ASIC or SoC EE Times

Adaptable Hardware with Unlimited Flexibility for ASIC & SoC ICs - EE Times

Adaptable Hardware with Unlimited Flexibility for ASIC & SoC ICs EE Times

Renesas licenses French embedded FPGA tech ... - eeNews Europe

Renesas licenses French embedded FPGA tech ... eeNews Europe

Unlocking the Power of Digital Twins in ASICs with Adaptable eFPGA Hardware - EE Times

Unlocking the Power of Digital Twins in ASICs with Adaptable eFPGA Hardware EE Times

Menta launches eFPGA soft IP - embedded.com

Menta launches eFPGA soft IP embedded.com

Menta Embeds FPGA Programmability - Semiconductor Engineering

Menta Embeds FPGA Programmability Semiconductor Engineering

Menta SAS eFPGA SOFT IP - Embedded Computing Design

Menta SAS eFPGA SOFT IP Embedded Computing Design

EU-Funded NimbleAI to Deliver 3D Neuromorphic Chip - EE Times Europe

EU-Funded NimbleAI to Deliver 3D Neuromorphic Chip EE Times Europe

Embedded FPGA used to tweak SoC design without re-spins - Electronics Weekly

Embedded FPGA used to tweak SoC design without re-spins Electronics Weekly

Menta eFPGAs Win Over E.U. - EE Times

Menta eFPGAs Win Over E.U. EE Times

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