Prashant Saxena Email & Phone Number

Scottsdale, Arizona, Us

Santa Clara, Ca, Us

Spearheaded the development and deployment of the first-generation LED driver system, leveraging the latest NexGen vertical GaN technology. Responsible for architecting definition of LED microcontroller, system/firmware implementation and backend system testing. Defined a scalable system architecture platform encompassing power densities ranging from 20W to 140W, employing optimized gate driver circuits tailored specifically for vertical GaN technology.* Industry’s first LED microcontroller flyback architecture which can achieve 1% dimming at 1Mhz switching frequency across universal voltage range.* Established system and test development teams in India and Australia* Passed all pre-certification compliance and regulatory requirements (surge, conducted & radiated EMI, ESD etc.)* Achieved >5W/in3 power density for a 20W LED driver system.

Neubiberg, München, De

Led the architecture and design development of In-Memory-Compute (IMC) SOC specifically tailored for AI hardware accelerators. Successfully managed and completed the tape-out of the first prototype silicon in this product family to demonstrate the inference capability.*Developed a novel and compact data path architecture specifically for the IMC (In-Memory-Compute) SOC to achieve 8bit accuracy.*Successfully achieved first pass silicon by demonstrating near digital inference accuracy on 3 layers CNN network using MNIST database*Developed innovative multi-bit programming algorithm for programming 128 states in a flash array

San Jose, Ca, Us

Strategic product ideation and chip development to capture high revenue SRAM business and retain market leadership (#1). Managed design and development process of embedded non-volatile flash macros.

San Jose, Ca, Us

Spearheaded the product line architecture and successfully managed chip/IP development process and customer support for low power and high-speed SRAM with ECC (65nm). From the initial conception to full deployment, seamless progression of the SRAM product was ensured, demonstrating strong leadership throughout. Served as the primary point of contact for resolving customer FA cases and identifying new opportunities for memory products.

San Jose, Ca, Us

As a program manager, successfully led the design of a 90nm 32M/64M asynchronous fast SRAM utilizing a stack die solution. Managed teams from cross-functional roles like FAB, assembly, packaging, backend testing, quality, design, and product engineering. Took charge as the IP lead for 10-bit SAR ADC IP blocks, overseeing all technical aspects, including post-Si IP characterization and seamless integration at the top level within a programmable SoC.

San Jose, Ca, Us

I began my career as a design engineer and worked my way up to become the tech/IP lead for all 90nm/130nm SRAM product development. During this period, I worked on many IP developments ranging from POR, IO, and both low and high-power voltage regulators. Worked extensively in pre & post Si activities.

Executive Mba

M.Tech, Solid State Physics

B.Tech, Electronics

Education record