A. V. Anil Kumar

A. V. Anil Kumar Email and Phone Number

Senior System Design Engineering Manager at Xilinx @ Xilinx
san jose, california, united states
A. V. Anil Kumar's Location
Bengaluru, Karnataka, India, India
About A. V. Anil Kumar

Experienced Engineer with strong technical skills in all phases of semiconductor development. Comprehensive knowledge of FPGA based designs with hands on experience on Design, Development, hardware validation and verification of complex FPGA based Socs. Specialities:- FPGA Design - Design creation from architecture, RTL Coding in Verilog and VHDL, Timing analysis and HW validation.- System level debug - Verification methodologies like SystemVerilog and OVM- Functional Simulation- Scripting for automation.- PCIe, Ethernet, AXI- SDH/SONET, PDH

A. V. Anil Kumar's Current Company Details
Xilinx

Xilinx

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Senior System Design Engineering Manager at Xilinx
san jose, california, united states
Website:
xilinx.com
Employees:
4650
A. V. Anil Kumar Work Experience Details
  • Xilinx
    Senior System Design Engineering Manager
    Xilinx Jul 2021 - Present
    Hyderabad, Telangana, India
    Leading a team involved in Emulation and Prototyping of Xilinx SOC products. The platforms delivered by our team enable functional & performance validation and also enable early SW development. Team also enables productive debug solutions & regressions to ensure the quality of the chip for multi-billion gate designs.
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  • Xilinx
    Systems Design Engineering Manager
    Xilinx Jul 2018 - Jun 2021
    Hyderabad Area, India
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  • Xilinx
    Design Engineer - Ii
    Xilinx Mar 2011 - Jun 2014
    Hyderabad Area, India
    Involved in Design, development, validation of Targeted Reference Designs for Xilinx FPGAs. These reference designs showcase the potential high performance capabilities of Xilinx FPGAs towards high speed interfaces like PCIe, Ethernet and DDR3.Involved in SystemVerilog and OVM based verification infrastructure development and enhancement for such complex designs.Updating and maintaining the reference designs with latest tools and builds, testing and package release to marketing team.
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  • Tejas Networks
    Senior R & D Engineer
    Tejas Networks Jun 2009 - Mar 2011
    Bengaluru Area, India
    Involved in design, development and testing of FPGA designs for SDH/SONET, PDH and Ethernet based applications. Responsibilities were RTL coding in Verilog, Functional Simulation, HW validation, System level debugging and Documentation of Design documents and test results, scripting for automation using Perl for regression runs.
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  • Tejas Networks
    R & D Engineer
    Tejas Networks Jul 2007 - Mar 2009
    Bengaluru Area, India
    Involved in FPGA designing for SDH/SONET, Ethernet and other telecom applications.
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A. V. Anil Kumar Skills

Fpga Verilog Soc Vhdl Debugging Systemverilog Xilinx Pcie Static Timing Analysis Rtl Coding Perl Ethernet Semiconductors Functional Verification Rtl Design Modelsim Asic Vlsi

A. V. Anil Kumar Education Details

Frequently Asked Questions about A. V. Anil Kumar

What company does A. V. Anil Kumar work for?

A. V. Anil Kumar works for Xilinx

What is A. V. Anil Kumar's role at the current company?

A. V. Anil Kumar's current role is Senior System Design Engineering Manager at Xilinx.

What schools did A. V. Anil Kumar attend?

A. V. Anil Kumar attended Indian Institute Of Technology, Delhi, Jb Institite Of Engg And Technology.

What skills is A. V. Anil Kumar known for?

A. V. Anil Kumar has skills like Fpga, Verilog, Soc, Vhdl, Debugging, Systemverilog, Xilinx, Pcie, Static Timing Analysis, Rtl Coding, Perl, Ethernet.

Who are A. V. Anil Kumar's colleagues?

A. V. Anil Kumar's colleagues are Mason Tsai, Eva Kuroiwa, Luan Ngo, Zoe Adams, Christopher Karman, Xilinx Eda Software, 朱小东.

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