Nov 2023 - Present
AeroLeads people directory · profile
Aakash Verma Email & Phone Number
Emulation @ Meta - MTIA
at
Meta
1 work email found
@intel.com
2 phones found area 213
LinkedIn matched
✓ Verified Jun 2026
4 data sources
Profile completeness 100%
Current company
Role
Emulation @ Meta - MTIA
Location
San Francisco Bay Area, United States, United States
Who is Aakash Verma? Overview
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Quick answer
Aakash Verma is listed as Emulation @ Meta - MTIA at Meta, based in San Francisco Bay Area, United States, United States. AeroLeads shows a work email signal at intel.com, phone signal with area code 213, and a matched LinkedIn profile for Aakash Verma.
Aakash Verma previously worked as ASIC Emulation Engineer at Meta and Lead Emulation Engineer at Intel Corporation. Aakash Verma holds Masters Of Science (M.S.), Electrical Engineering (Digital Vlsi And Computer Architecture) from University Of Southern California.
Company email context
Email format at Meta
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{first}.{last}@intel.com
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Profile bio
About Aakash Verma
Electrical Engineer with extensive experience spanning Emulation and SoC Pre-Si Verification targeting Functional & Power Verification.• Skilled in Emulation tools, flows and methodologies for HW verification and SW/Firmware development.• Adept in UVM, Object-Oriented SystemVerilog, Verilog, Verdi, DVE, Eclipse DVT, C++, and Testbench Architecture with working knowledge in Python.• Experienced in Digital RTL design & Micro-Arch Specification, Low-Power methodologies, Chipset SoC Architecture involving multiple Low/High Speed I/Os.
Listed skills include Vlsi, Verilog, Logic Design, Microcontrollers, and 44 others.
Current workplace
Aakash Verma's current company
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9 roles
Aakash Verma work experience
A career timeline built from the work history available for this profile.
Lead Emulation Engineer
- Leading Emulation and Post-Si validation activities for P4 based Tofino line of Programmable Network Switches.- Emulation for Intel eASIC & FPGA Product Line
Jan 2021 - Nov 2023
Staff Design Verification Engineer - Emulation
- Emulation and FPGA Prototyping technologies for ThunderX family of ARM processors in Server Processor Business Unit focusing on Cadence Palladium platform.
- Lead the Emulation activities for Marvell’s ThunderX family of ARM processors on Cadence Palladium Z1 platform.
- Responsible to develop Emulation infrastructure and enable automated flows for design compilation (ICE flow) and runtime as well as releasing emulation RTL builds with different configurations for SW/Firmware.
- Booted Linux OS on server chip emulation build and debugged several logic, firmware, and tool issues to enable early software validation, driver development, and test performance benchmarks. Collaborated closely with.
- Developed/Modified SystemVerilog RTL behavioral constructs and testbench for Emulation modeling and efficient performance, fixing synthesis and utilization issues for accelerated execution.
- Integrated and verified vendor models for multiple interfaces like HBM, DDR5 [PHY & Memory], PCIE Gen5, SD card, SPI Nor Flash, and worked closely with vendor AEs and R&D teams to mitigate multiple tool issues and any.
May 2019 - Jan 2021
Senior Design Verification Engineer (Soc Pre-Si And Emulation)
- Responsible to verify functional and power-saving features at IP & SoC level for multi-generation Platform Controller Hub (PCH) Chipset SoC targeting Server, IOTG, PC and mobile markets.
- Developed test-plans, test cases in UVM/System Verilog, SV assertions & functional coverage to check design compliance with the architectural specs for various blocks at SoC like PLLs, PHYs, Voltage Regulators, and.
- Verified reset/boot-up flows at SoC and protocols like USB, SATA, PCIE, GBE at interface level on a partition-based UPF SoC model with multiple voltage rails and power domains.
- Developed and modified existing testbench components like monitors, scoreboards, interfaces and overall environment.
- Lead TR (technology readiness) activities for a future project namely feature evaluation, project scoping and resource distribution. Contributed exhaustively in verification enhancement primarily stub-modeling.
- Devise new capabilities and enhance existing for HW/SW components like testbench DPI transactors, runtime software in System Verilog/C++ and integrate them with the emulation model for streamlined testing and.
Sep 2014 - May 2019
Microprocessor Logic Design
- Responsibilities included developing RTL for performance features for the Instruction Decode Queue in the Front-End (FE) Cluster for 10nm Intel Core CPU that involves coordinating the efforts between RTL, validation.
- Lead the Formal Equivalence Verification (FEV) – Syn2sim for the Front-end cluster.
Jul 2013 - Sep 2014
Component Design Engineer (Cad Engineer Intern)
- Developed various Quality Assurance (QA) checks & Automation Scripts in PERL to automate Standard Cells, Parasitic Extraction Flow and Auto Place and Route (APR) Flow for the next-generation SSD memory.
- Developed GUI for Parasitic Extraction Netlisting (StarRC) using SKILL scripting language for Cadence that is included with the existing options in Virtuoso IC 6.1.5 (Open-Access).
Jan 2013 - May 2013
Student Worker At Usc Housing
Managing the inventory database at Housing Office and directly dealing with the Manager.
Aug 2012 - Dec 2012
Project Trainee
- Project: Iodine Cell Temperature Control System
- Built the microcontroller (Atmega 16) based hardware system monitoring and maintaining the ambient temperature by switching the heater around the Iodine Cell, used in the optical arrangement of sky observation.
- It was part of PARAS, India’s first exo-planet search program and stationed at Mt.Abu Observatory, India.
Jan 2011 - Apr 2011
Trainee
Worked upon the basic aspects of MSP430 microcontroller by Texas Instruments, incorporated by Masibus in the RTU (Remote Terminal Unit) of the project funded by Siemens Ltd. India.
Apr 2010 - Apr 2010
2 education records
Aakash Verma education
Masters Of Science (M.S.), Electrical Engineering (Digital Vlsi And Computer Architecture)
University Of Southern California
B.E, Electronics And Communication
L.D. College Of Engineering
FAQ
Frequently asked questions about Aakash Verma
Quick answers generated from the profile data available on this page.
What company does Aakash Verma work for?
Aakash Verma works for Meta.
What is Aakash Verma's role at Meta?
Aakash Verma is listed as Emulation @ Meta - MTIA at Meta.
What is Aakash Verma's email address?
AeroLeads has found 1 work email signal at @intel.com for Aakash Verma at Meta.
What is Aakash Verma's phone number?
AeroLeads has found 2 phone signal(s) with area code 213 for Aakash Verma at Meta.
Where is Aakash Verma based?
Aakash Verma is based in San Francisco Bay Area, United States, United States while working with Meta.
What companies has Aakash Verma worked for?
Aakash Verma has worked for Meta, Intel Corporation, Marvell Semiconductor, University Of Southern California, and Physical Research Laboratory.
How can I contact Aakash Verma?
You can use AeroLeads to view verified contact signals for Aakash Verma at Meta, including work email, phone, and LinkedIn data when available.
What schools did Aakash Verma attend?
Aakash Verma holds Masters Of Science (M.S.), Electrical Engineering (Digital Vlsi And Computer Architecture) from University Of Southern California.
What skills is Aakash Verma known for?
Aakash Verma is listed with skills including Vlsi, Verilog, Logic Design, Microcontrollers, Systemverilog, Rtl Design, Computer Architecture, and Universal Verification Methodology.
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