✤ On-boarding of the IPs/VIPs with Rocket Chip via SiFive on-boarding flow✤ Lead for the development of VIPs (OSPI (Master and Slave), RTC and eMMC) using UVM✤ C-Tests Development, Deployment and Verification

✤ Development of VIPs for OSPI and QSPI using Universal Verification Methodology✤ On-boarding of the IPs/VIPs with Rocket chip using SiFive flow✤ Development of Testplan for LPDDR4

✤ Development of VCS compilation and configuration flow for Pulpino SoC using PULP platform✤ Development of Modelsim compilation and configuration flow for Pulpino SoC using PULP Platform✤ Team Lead for Berkeley out of order machine (BOOM) Optimal Configuration and Verification✤ Team Lead for 3-Stage Pipelined RISC-V processor for RV32I and RV64I written in Chisel✤ Team Lead for Instructions Set Simulator (ISS) Design and Verification with respect to SweRV EH1 core✤ Team Lead for SweRV EH1 Integration and Code coverage via Google DV✤ Development of Verification environment for 4x1 Router Switch in System Verilog✤ Development of Functional Verification environment for Wishbone Slave Interface using SystemVeri-log✤ Design of Single Cycle RISC-V processor in Verilog for RV32I

✤ Citizen portal Management✤ Registration campaign and assessments✤ Recognizing and addressing the issues in registrations