Managed and developed the architecture, quality, and content of Sort and Class test programs from pre-silico vector and test program development through high volume manufacturing to PRQ and post-PRQ sustaining including, End of Life Testing, Cold Socket Elimination and Product Sustaining to handle process shifts and other yield impacts. Mentored and Trained Product Development Engineers on my team for the particularities of each project. Developed and published: hardware configurations, test program conventions, flows, and best know methods for each project based on product requirements. Owned the overall test program and provided expertise, framework, conventions, and methods for content owners on Intel® Optane™ Persistent Memory (PMem) and Intel® C112,C114,C102,C104 Scalable Memory Buffers. Managed test hardware development, including special circuit design and hardware configurability to handle various debug configurations that could be required to work around new DFT (Design for Test) functionality. Planned and arranged the labor, schedules, and equipment required for correlation and volume data collection runs on test floors allowing daily feedback to the team. Reports provided give a clear picture of progress and work needed to meet the next test program release goals. Improved efficiency, automated tasks, and optimized test time, meeting and exceeding all product health indicators. Provided task force leadership to resolve showstopper issues.

Delivered quality content for Sort and Class test programs from pre-silico vector generation to hardware design to software development. Team player, always willing to help and train other PDEs to insure their success and the success of the project. Owned DDR, Fuse, IDV, Parametric, Basic Functional content, meeting or exceeding coverage, test time, yield, and stability requirements. Delights in the disassembly of complicated tasks and methodically coming up with innovative solutions. Designed test hardware, including probe cards and load boards with all required debug features, configuration options, and special circuits. Quickly became the go-to-guy for scripting, code modification, and data collection needs. Took over the Sort test program for B1 Si with PHY goals in jeopardy, implemented a 37% test time reduction in test time good allowing team to meat PHI goals and relieve tester capacity constraints that plagued previous steppings. Was able to drop the test time below the probers index time of 2s (2005-2006 INTEL® 82566MM,MC,DM,DC GIGABIT ETHERNET PHY)