Aaron Leclaire Email & Phone Number

San Jose, Ca

Cupertino, Ca

• Architect and design IP for video interfaces, video processing, and video transport via PCIe. • Video Interfaces include: HDMI, DP tunneled over Thunberbolt, DP-alt mode via USBC, and CoaxPress.

• Network Interface Card FPGA architect and developer. Design includes RDMA, QoS support, DMA completion status queues in system memory, and statistics gathering.• Network switch FPGA architect and developer. Cut-through architecture for low latency messaging.

• Architected and designed FPGA hosting a 4K120 video path that includes DisplayPort 1.2 multi-streaming inputs, 4K up and down scalers, frame rate converters, a PCIe streaming frame capture subsystem, and a Vx1 output to the panel.• Designed a clock recovery subsystem for DisplayPort inputs.• Managed consulting groups, including Bitec and Omnitek.• Worked closely with GPU vendors AMD and nVidia.

• VHDL design starting from C++ models.• Verification using SystemVerilog and UVM, constrained random stimulus, score boarding, assertions, and functional coverage.• Developed bus functional models for AXI, APB, and other interfaces.• Developed test routines in C for evaluating the RTL on a FPGA test platform.

• Architected an audio/video communications system for the medical market that supports multiple A/V standards via a low latency, secure 10GbE link. Collaborated with customers and marketing; published detailed architecture and financial documents for the business case review. • Architected FPGA with DisplayPort, PCIe Gen2, de-interlacer, scaler, packet processor, traffic manager, AES128 encryption engine, and 10GbE link via XAUI. • Authored funding application; successfully secured ~$250,000 government grant for research in the area of medical communications.• Architected and developed VHDL code for a high performance, FPGA based graphics controller. Wrote self checking verification suite using score boarding techniques, bus monitoring, and results logging. Project completed on schedule and design exceeded performance goals. The design was highly leveraged, resulting in reduced inventory levels, simplified materials management, and increased production efficiency. Material costs were reduced by 50%. • Developed a display that operates in a 4 Tesla magnetic field and produces very low emissions. • Various PCB designs including embedded processors, power, FPGA, DDR2/3, PCI, PCIe, DVI, DisplayPort, etc.• Led the outsourcing of various pieces of IP to LabX, Omnitek, and NW Logic.• Prototyped architecture concepts early in design cycle. • Managed projects with international teams.• Collaborated with customers domestically and internationally.

• Team Lead and Hardware Architect for Mixed Signal Instrumentation Group.• Focused on the use of SERDES, and FPGA development.• Received "Exceeds Expectations" for all reviews.

• Responsible for multiple large circuit boards and FPGA subsystems.• Architected and designed a PCI bus master with 4 chainable DMA engines, and a PCI target capable of multiple posted writes and a single deferred read.• Received "Exceeds Expectations" for all reviews.

• Member of the system architecture team for the Profile Disk Recorder, used primarily for video cache, non-linear editing, instant replay, and mix effects• Architected and designed a SDTI IO board supporting DVCPRO.• Responsible for multiple FPGA and PCB designs.

• Designed the analog audio path in Motorola's first digital mobile phone.• Specialized in audio quality, power supply issues, and design for manufacturability.

Ms, Electrical Engineering, 3.8

Bs, Electrical Engineering, 3.6