Aashka Patel Email & Phone Number

Over 9+ years of experience in the field of ASIC Design Verification.• Successful completion of multiple ASICs starting from defining test bench architecture to coverage closure.• Hands on experience in developing UVM and SV based Verification Environment.• Working experience of PCIe Application Layer, Transaction Layer and Data Link Layer.• Verification experience of NVMe based Enterprise SSD ASICs.• Experience on working at different stages of verification i.e. Unit/Block level, Sub-system level and Chip/Top level.• Worked on developing Bus protocol checkers and Transaction Level Modeling.• Experience in developing Reference Model.• Modeling experience for MIPI (Mobile Industry Processor Interface) MPhy (Mobile Physical Layer) Protocol.• Hands on experience in Functional Coverage and System Verilog Assertions.• Verification experience of 3-D Graphics Processor Unit.

Listed skills include Asic, Uvm, Soc, Functional Verification, and 18 others.