More to be announced

Teaching Computer design and architectureSupervising and mentoring graduate students in PhD-level research

Developing a portfolio of services that enable our Enterprise customers to unlock business value from public cloud.

Flux7 was acquired by NTT Data Services on December 30, 2019.

-Create a scalable platform for system-level performance and power analysis of ARM based microservers-Develop a distributed benchmarking environment to automatically collect and log performance results. (created a frontend GUI in HTML5 and Javascript)-Optimize and run industry standard benchmarks on Calxeda and Intel hardware. Benchmarks include SPECint, SPECjbb, SPECjvm, SPECpower, Coremark, Stream, FIO, IOzone, other tests from phoronix-test-suite, and in-house app-tier, web-tier and storage-tier benchmarks-Project performance of BigData platforms like Hadoop, Ceph, Gluster, Sector/Sphere, Cassandra, CouchDB, MongoDB, and Node.js on future generations of Calxeda and Intel competitor -Developed an internal benchmark for receiving and broadcasting real-time news in node.js (similar to the Bloomberg terminal)-Collaborate with marketing to establish Calxeda's value proposition in the context of power efficiency, compute density, total cost of acquisition (TCA) and total cost of ownership (TCO)-Liaise with performance engineers at partner OEM's and end customers-Help in recruiting and establishing relations with academic researchers

I was responsible for technical oversight, technical marketing, thought leadership and branding, roadmap development, and coding parts of the application. Led a team of two engineers. At Cymulate, we were building technologies to aid cross-platform mobile development using PhoneGap (now Cordova). We build a framework for rapid debugging of iOS and Android apps via PhoneGap that sped up the code-compile-deploy-test process by over 10x. We also built a framework similar to PhoneGap Build for Android apps that supported creating Android apps with custom plugins (a feature not available in PG build at that time). Lastly, we build a benighted similar to WineRe, albeit faster and more stable. It was built on top of node.js and socket.io.

-Architected Intel Xeon Phi, specifically the coherence interconnect and instruction decode units. We designed Xeon Phi for massive throughput for Graphics and HPC workloads. Xeon phi is the first many-core Intel chip with 62 in-order cores. Each core has 4 hardware threads, a two-level private cache hierarchy, and a 512-bit wide SIMD unit. -Maintained and extended a multi-threaded multi-core performance simulator for Xeon Phi-Formulated the process to benchmark GPUs.-Investigated innovative paradigms for parallel programming.-Researched techniques to improve load-balancing in multi-threaded applications.-Ported simulation infrastructure to the Amazon Elastic Compute Cloud.-Investigated software techniques to reduce data synchronization in irregular applications.-Studied hardware techniques to reduce the impact of critical sections on performance.-Developed a distributed job scheduler for Windows XP compute clusters.-Parallelized applications to evaluate the trade-off between hardware- and software-efficiency.-Implemented directory-based cache coherence in the multi-threaded/multi-core simulator.-Hired/mentored new employees and interns for simulator/scripting projects

-Proposed a scheduling policy to reduce cache warm-up effects in TPC-C.-Studied memory interference experienced by concurrently running transactions.-Added improved checkpointing support for JAVA benchmarks.

-Developed tools to identify instructions from each transaction in TPC-C.-Analyzed instruction and data footprint of each transaction type.-Ported a suite of multithreaded benchmarks in the simulation environment.

-Maintained and enhanced test solutions to reduce cost and increase test coverage.-Supported RMA analysis including verification, failure analysis, corrective action, and documentation.-Formulated test plans and strategies.-Liaised with OEMs and testing facilities.

-Conducted test audit for digital I/O and timing hardware. -Verified test coverage and implementedtests to increase coverage.-Tested and Debugged RMAs and Dead-On-Arrival (DOA) boards.-Reviewed board-level and ASIC designs of products under development.