Digital IC Design and Verification TrackThe training gives expertise in digital design flow for ASIC including Verilog modeling, synthesis, minimization, standard-cell libraries, timing optimization, timing models, timing analysis & constraints, Clock Tree Synthesis, placement and routing, Signoff and chip finishing, and design for testing. Regarding the verification and testing of digital systems, the SystemVerilog concepts such as Data types, Functions, threads, Interfaces, randomization,… Show more Digital IC Design and Verification TrackThe training gives expertise in digital design flow for ASIC including Verilog modeling, synthesis, minimization, standard-cell libraries, timing optimization, timing models, timing analysis & constraints, Clock Tree Synthesis, placement and routing, Signoff and chip finishing, and design for testing. Regarding the verification and testing of digital systems, the SystemVerilog concepts such as Data types, Functions, threads, Interfaces, randomization, Code Coverage, Functional Coverage, and Assertion Based Verification are covered. In addition to OOP and Hierarchal Testbenchs. UVM verification projects include components such as transaction, generator, configuration, sequencer, driver, monitor, …. also, faults in digital systems, test generation and testable systems, and pattern generation and comparator circuits of the built-in self-test. In addition, the VLSI and full custom IC design flow topics learned include the design of complex digital circuits, PLA, Arithmetic Blocks, Memory Design, system interconnect, Clock Generators, and System Level Integration and it emphasizes principles such as power optimization, timing analysis, and signal and power integrity issues. These modules are delivered by worldwide industry experts and university professors. Through hands-on experience in the labs with industry-standard CAD tools, the trainee successfully completes assignments and projects for each course.CAD tools include: Synopsys’s flow (Design Compiler, Formality, Library Manager, ICC2, PrimeTime, VCS, Verdi), Siemens’s flow (Tanner EDA: S-Edit, L-Edit, W-Edit, Calibre), Questa, Intel’s Quartus, and Cadence Virtuoso.Languages: SystemVerilog, Verilog Show less

PnR internship that focuses on how to convert an RTL design to a physical design.

Digital Design Functional Verification Diploma consisted of:• Some scripting techniques using python and bash.• Using Verilog and System Verilog in design and verification.• Advanced FPGA debugging capabilities.• Quality assurance techniques and software testing.

Instructor, IEEE CUSB (Cairo University student club branch)• Instructor in the digital electronics committee.• Teaching Verilog and FPGA design.