Acquired practical, hands-on experience in digital layout design, where I created complex schematics and layouts for CMOS circuits using advanced tools such as Synopsys and Custom Compiler. I successfully completed more than 25 schematic and layout cells, including essential digital components like logic gates, multiplexers, flip-flops, and latches, implementing 28nm and 14nm FINFET technologies. Throughout these projects, I developed a strong proficiency in Design Rule Checking (DRC) and Layout Versus Schematic (LVS) verification, which were critical for ensuring design integrity and functionality.In addition to technical design work, I have refined my debugging skills, allowing me to identify and resolve issues efficiently at each stage of the design process. My experience also extends to a solid understanding of fabrication flows, as well as advanced layout design flows and techniques, which have further enhanced my capabilities in high-precision digital layout design.