• Managed 19 direct reports within two critical manufacturing post-silicon SLT validation teams: Processor Platform Validation (PPV) & Circuit Marginality Validation (CMV); both teams support Intel's Server products (Xeon) roadmap. • Led the PPV team to release one of the high-volume manufacturing socket test programs in different test-facilities across the globe and made sure to reach the target of the Product Health Indicator (PHI: yield, retest rate, test time good, defect per million [DPM] etc.) for each product. • Provided guard band by evaluating system to tester (S2T) miscorrelation of Vmin for the product's correct binsplits; made sure there were no marginality issues of the products shipped to the customers through CMV works of speed binning, resolving critical speed path issues and optimizing Vmin. • Introduced power management content in Circuit Marginality Validation (CMV) test suites to close Vmin sensitivity in providing accurate guard band recommendation. • First introduced fixed rail CMV validation in Intel where fixed rail cross domain marginality observed on dynamic rail when the fixed rail was configured with IOs (PCIe/UPI) while running concurrency contents.• Supported High Volume Characterization Platform (HVCP) efforts improving the quality of server products. • Automation development towards boosting the accuracy and efficiency of multiple functions/products across multiple sites to save countless engineering hours & emulated "one company mindset".• Best utilization of headcount resources by optimizing the tasks of multiple functions of HW infrastructure, BKC, debug, initial pre-Si strategy & planning using key resources.• Drove collaborative works on SLT across most Intel sites including Malaysia, Santa Clara, Oregon, Costa Rica, Israel etc. • Worked to build skill matrix for the career growth of 19 team members. • Drove all segments of Intel product development such as Server, Client, Device & Modem

• Managed CMV team for guard-band recommendation for client & server products• Engaged with Class/Component Debug teams to improve system to tester miscorrelation by examining limiter seeds• Engaged with FV/IFWI/BIOS/PnP for enabling Client product• Involved working on 1% Marginality Detect to ensure quality GB• Checked PM marginality as CMV in general don't do PM marginality & implemented necessary measures.• Support relevant DOEs for quality GB for server product.

• Drove Processor Platform Validation (PPV) team for test program release of client & server products in the factory• Managed Circuit Marginality Validation (CMV) team for guard-band recommendation for client & server products• Drove Device per Million (DPM)/Test Hole Reduction (THR) team for tracking the DPM though Manual Reject Validation (MRV)• Some of the accomplishments:o Server Product: Achieved Product Release Qualification (PRQ) on server product on time through overcoming lot of challenges including VR on the fly, PCIe etc., beat PHI expectation of TTG in PPVM, improved yield. Received huge appreciation from upper management along with DRA recognition.o Client Products: Released Test Program every alternate week on multiple client products, PRQ’ed the products on time. Released the challenging job of fungibility to the factory across multiple products which saved one conversion wastes up to 17,280 cell hours or 130K units tested. Team received DIA recognition.o Team released Smart PPV on client product for Test Time Good (TTG) reduction to meet PHI goal, received DIA recognitiono Team worked with Israel team to move clien products from Fusion to Legacy automation and beat PHI expectation on TTG and received DRA recognition along with Israel team.

• Combined the CMV and DRC scrum teams into one Austin-MDC scrum team and inspired and assigned most of the team members for both roles for the maximum utilization of the team resources.• Demonstrated an excellent development, execution & leadership capabilities in the key accomplishments for all segments of Intel products like Client, Modem, Device, Server.• Took the challenge of taking the ownership of one of the client products in the middle of Qualification Samples (QS) execution from Israel team. The challenges the team overcame included cross site collaboration, hardware and knowledge transfer, learning a new product line in the middle of QS execution and ensuring to deliver quality results while meeting the deadlines.• Team received 11 Divisional Recognition Award (DRA) during 2018 for the outstanding Intel business contribution• Team quickly ramped up, validated completely new sets of test contents/patterns in class regression. Those test patterns were running against rejects and started catching DPM rejects. The patterns which were found effective to catch rejects are being ported to class TP. The effectiveness of those patterns is being tracked through per pattern tracking tool.• Worked with other MDC managers and set example of collaboration. My team is always engaged with either on-train or off-train works.

• Took the responsibly to build the Austin CMV team• Took initiative to hire qualified candidates for Austin-Functional Validation teams; traveled to OR & CA for attending Red Carpet Hiring Events.• Provided GB for device products towards PRQ• Team supported to find the root cause of a critical stop-ship issue involving in a device product of SoC Si Bug and released a FW patch to resolve the issue with minimal impact to the customer, an outstanding outcome given the complexity of the issue and team member received a DRA recognition.• Pulled in for debug support of a modem product; enabled the platforms, test contents, automation within possible shortest time and completed timely validation for Tape-In. Team received MAA recognition.• Team was pulled in to debug a bin split issue of a server product and was able to get a System Validation based CMV solution and automation working and helped in closing the issue and the team members were awarded an MMA recognition for the work.

• Built the Austin TPV team from scratch• Motivated the thermal team such a way that the whole team along with other member from PPT team wanted to move to the new TPV team and the management put restriction not to hire any person from PPT team within 6 months.• Took the responsibility for filling out the team, defining R&R, acquiring lab space, and working with key contacts on a plan to ramp up the team as fast as possible.• Supported TPV tasks for device products simultaneously towards PRQ.

• Built the PPT thermal team from scratch and made it one of the best thermal team across Intel.• Supported 4 simultaneous device projects at one point before taking the responsibility of AN TPV manager role.• Led System Validation Engineering (SVE) commonality PPT thermal working group across all segments of thermal validation (Devices, Server, uServer and Client) and developed a common unified test plan and thermal methodology document.

 Test development and implementation: Developed test solutions for new products from first silicon to full production. Also responsible to define, document, analyze, perform test developments for modified/derivative products along with customer return products to detect the failure mechanism. Customer support: Supported customer returns (RMA) on products by electrical failure analysis testing and investigating the problem identification, root cause analysis and containment actions together with FA & QA group. Problem solving initiatives: Involved in the investigation and resolution of operational problems in conjunction with design, application, validation, quality assurance, marketing engineering. Productivity: Implemented cost-effective methods of testing and troubleshooting for high volume products. Test and process improvement: Monitoring production test results and identifying the top priorities to drive test and process improvements for high volume products.  Product specifications: Involved in the preparation of data sheet specifications by providing data for key test parameters. Product qualifications: Provided new product qualification by designing qualification hardware (burn-in/THB/HAST boards) and verified those on the bench setup.  Product characterization: Developed and performed characterization on new parts along with the derivatives for data sheet specifications & production test limits. Project risk management: Putting test guard-band, required CPK value & FIT measurement along with QA. Matrix lot analysis: Characteristic improvement of the product line by analyzing matrix lots data of new products and provided necessary recommendation to the fab. Exclusion zone in the wafer: Implemented exclusion zone in the wafer map by analyzing composite wafer map with the data of several wafers of high volume products.

Responsibilities includedHelped in developing leading edge semiconductor embedded NVM technology.Verified and established process standards using Communication Design Rule 3 (CDR3) for NVM.Characterization, qualification and failure analysis of embedded flash memory in package level.Cycling test to observe the effect of Program/Erase cycling rate on Low Temperature Data Retention (LTDR).Carried out CDR3 LTDR Split Evaluation and Process Spilt Evaluation test to observe LTDR behavior on different trench liner and pad oxide undercut.Hot Electron Injection evaluation for LTDR behavior.

The research work included Design and verification of operational characteristics of DC-DC Converter using MOSFETs under radiation environment for space technologies. The experimental results were verified by PSPICE simulation.Involved in project to verify the design of VLSI SRAM ICs using PSPICE simulation and MAGIC CAD layout DRC tools. This design was also carried out by PSPICE simulation to obtain and verify necessary time constant for each of the capacitors connected to 4 input NMOS drivers. Also worked to design a fixed-point implementation algorithms for a class of orthogonal polynomial filter structure using Matlab. A Huffman Source-Coding Algorithm was designed by C program for the compression of information sources.

Involved as an instrumentation and control engineer in the design, implementation, test and analysis of control and instrumentation system in research reactor facility. Also involved in design modification, test data analysis of control system including power supply, RTD, fuel temperature, percent power module, and control panel of stack monitor. Involved in monitoring the maintenance work of sub station, Area Radiation Monitor, Continuous Air Monitor, Stack Monitor, all electrical motors in the facility including primary and secondary cooling system, cooling tower, normal ventilation and emergency purging system, associated magnetic contact and relay etc. Involved in technical proposal writing including time and cost estimation to upgrade the instrumentation and control system of the console and reactor delay tank and all necessary equipment/parts for the facility.

The research work included Calibration and verification of functionality of Resistance-Temperature Devices (RTD), Continuous Air Monitoring (CAM) system, fuel temperature channel. Control rod drop time measurement.Efficiency measurement of emergency purging system etc.

Operation and Maintenance Engineer, 100 MW Gas Turbine Power Plant: Involved in the operation of the power plant. Maintenance of Generator, Turbine, and design modification of Cooling System, Fuel System, Air System and other supporting systems.Shift Engineer, Load Dispatch Center (LDC): Efficient Distribution and dispatch of power throughout the country. Monitor overall power transmission and take necessary action in the event of power shortage/outage. Forecast daily load requirements for the entire country and maintain close contact with all the generating units throughout the nation.