Architecture Modeling and exploration of Machine Learning, Ray Tracing and Shader subsystem features.

• Working in Reality Labs Research on Codec Avatars, train Deep ML models for realistic face and full-body avatars. Used conditional variational encoder and differentiable rendering to train a model to render avatars • Implement custom low power hardware for NN acceleration. • Neural networks for Graphical applications. Research new architecture for AR/VR applications.

• Taped out Opportunistic write-back discard of single-use vector register values in RDNA IP.• Primarily working on shader and texture; Evaluate and implement new architectural features, performance modeling and debug on C++ clock driven simulator; Identify issues with the compiler.• Developed tools to identify hotspots in GPU programs, identify canned patterns in programs, identify opportunities for hardware acceleration, manually schedule instructions with automated register allocation, extract dynamic counts of instructions, project performance with new instructions. • Proposed HW changes to reduce traffic, power and improve performance. Provide performance estimates by prototyping in arch model and provide power & area estimates. Perform ISA updates.

• Performance projection for future architectures using Speed of Light models; Developed multithreaded python framework to project GPU performance by exhaustively evaluating different combinations of throughput of units inside the GPU• Debug benchmarks in C++ clock driven model to improve performance.• Proposed driver, compiler, and hardware changes to improve performance in benchmark by 5.5%

• Implemented HSR in event based functional model in C++, performance modeling and debug using C++ clock driven model. Performance projection using throughput model• Developed performance models by understanding architecture and micro architecture specifications; Design and implement directed tests; Validate performance against RTL• Performance debug of tests and benchmarks on GPU top; Functional debugging for hardware bringup; Python scripts for automation

Developed a FPGA based Ray tracing Accelerator• Logic design of hardware for accelerating Ray Triangle Intersection(RTI) tests using mixed implementation of RTL and hard floating point IP on Arria 10. Used HLS for prototyping• The code was designed to be scalable, uses temporal multithreading to increase pipeline utilization and to overcome memory bandwidth limitations. Integrated the accelerator with a software Ray Tracer PBRT • Implemented RTI using AVX2, got a 10x speedup over single core• The hardware performed 1.3 billion RTI tests/sec, giving a speedup of 50x over single core Xeon

• Developed framework for automated sever deployment in Amazon AWS using python Fabric. Worked on python and Java based graphical web and server application.

• Designed and developed an Atmega 128 controlled Fire Alarm and interfaced it with GSM module, landline, audio message recording and playback using PWM, SD card using SPI, RTC using I2C.

• Developed a system to remotely monitor and control engine test beds• LabView based PC software to communicate with the PLC, program for AC-31 Programmable Logic Controller to remotely control the AS-800 AC drive used in Engine test beds