-Managed Engineering teams including ASIC, AMS, System, Packaging, Photonics, Runtime, and Machine learning.-Led the development of Photonic Fabric Compute SoC and drove tapeout of multiple testchips to demonstrate the photonic solution to key customers.

Hired as employee number 3 in a early stage startup. Responsible for managing all Silicon design, CAD, Verification and System design/development, Successful in growing the team to over 20 members. Role involved presenting Hardware Engineering plans and status at quarterly board meeting, supporting pre-sales technical engagements, leading engagements with silicon foundry, packaging houses and EDA tool vendors2018-2021:SoC (company's first AI/ML Edge Inferencing SoC and system)----------------------------------------------------------------------------------- Led all aspects of Silicon (RTL-> GDS), Verification, Characterization and Validation of the company's first 16nm Edge Inferencing SoC product offering called “InferX”. In addition to silicon design, managed verification, DFT, substrate, board development and all post-silicon validation and test of the SoC and hardware system. The A0 silicon has successfully passed silicon characterization and is ready for volume ramp. The PCIe based card is being sampled by lead customers. 2015-2021:eFPGA IP Design & Volume Ramp--------------------------------------------------- Main responsibility was to build a hardware design team which is responsible for taking design from RTL definition to GDS, post silicon test and validation and to ensure the prototype product is ready for high volume production. As part of this effort, I defined the Validation Chip architecture used for prototyping and testing the eFPGA silicon. Coded the design using RTL. Managed emulation and built the system lab with bench equipment to validate the silicon across process, voltage and temperature. Worked with vendors to build and package the device. In addition to engineering, I was the primary customer technical lead on all the eFPGA back end silicon design and integration till Jan 2018

2014-2015:Memory Products-Technical lead for next-gen DDR4 Memory Register and Data Buffer used in server and HPC systems-First product launched by the company as part of it's growths strategy. Devices sampling starting 2H 2015-Responsible for technical product definition and for driving external customer requirementss across a large cross functional, multi-site effort across silicon, verification, systems, signal integrity and marketing teams to ensure design meets product definition and customer requirements -Primary technical interface with Intel, Samsung, SK-Hynix, Micron and OEMs such as Dell, HP, Lenovo, Oracle and leading ODM's in driving adoption of this new product -Additional responsibility includes working with R&D division to define future memory roadmaps2012-2014: Memory & Serial PHY IP -Responsible for pre-sales technical support for Serial and Memory Links -Drove adoption of PHY IP at 28um & 14nm nodes with a large ASIC foundry -Established relationship with Digital Controller IP companies to provide a complete solution of Digital Controllers and Link layers to end customers-Worked closely with customers and internal engineering design teams from US and India design centers to define IP product requirements, architectural definition, technical feasibility and process node selection

-Headed the Rambus India Development center. Primary responsibilities were to manage the operations of the India site and the engineering ogranizations. The engineering team included two mixed signal design teams, one system design team, one digital controller team, one CAD team, two verification teams and one software team-Managed a total of 100 employees at the design center. Worked with US based executives to drive annual operating goals as well as the engineering goals for the worldwide engineering organizations.-Responsible for local management of all support functions such as HR, Finance and IT teams. Managed the India Design Center annual budget, participated on Rambus India Board of Directors, managed local governance laws and managed all the recruiting activities for the site.-Responsible for projects designed and developed at the India design center as well as for deliverables for projects where the India teams were part of the worldwide design team.

-Responsible for managing two mixed signal teams, one custom CAD and one P&R team. Successfully released multiple IP products in 65nm technology node.-Each project included management of all post-sales activities from product definition to silicon design to characterization-Led the effort of interfacing with the customers based in Japan & US and managing cross-site teams where silicon design, verification and characterization teams were based in India and package, system, signal integrity and program management teams were based in the US

-Helped establish Rambus India Design Center and was the primary nucleus that motivated Rambus to start the remote design center. As part of this assignment I moved to India and was responsible for hiring and technical development of the design teams.-The India center started out as a team of two people and over the next two years I built up the team to 30 engineers.-Established relationship with premier engineering universities in India to create a Rambus brand to attract the best and brightest graduating students.-Managed the setup of engineering characterization and signal integrity teams in our India center.-Led two successful customer tapeouts in TSMC 130nm and 90nm technology nodes.

-Responsible for management and delivery of the next generation memory controller interface called XIO which was included in the IBM Broadband Engine (BE) CPU for the Sony PS3 game console. This was the first product developed and shipped in volume for the XIO interface and I was involved in hands-on technical development, product bring-up and silicon validation efforts.-Managed a team of 12 circuit, digital and layout engineers to design the XIO interface in IBM SOI 90nm technology-Lead technical interface to IBM, Sony and Toshiba which included weekly cross-company development meetings ultimately leading to the successful bring-up of silicon in customer reference platforms.-Managed the design effort for development of the XIO interface. This effort included design, tape-out and characterization of the 2 silicon test-chips in TSMC90nm process. The test silicon developed was used in pre-sales meetings to demonstrate technical feasibility of the XIO interface to customers including Sony, Toshiba and Samsung

-Managed the digital logic design team. Responsible for RTL design, P&R, static timing analysis and mixed signal simulations

-Lead logic designer for the RDRAM memory interface. In this role, I designed the entire logical interface for the Direct RDRAM memory and interacted with circuit, system and verification engineers.-Post silicon design, responsible for the logic section of technical transfer of the reference design to eight memory partners including Samsung, SK-Hynix and Micron.-Involved in debug and characterization of silicon from multiple memory vendors. The effort led to successful launch of the Direct RDRAM memory in volume.

-Responsible for designing the company's first ASIC controller chip as well as design of a multi-chip module (MCM) housing the ASIC controller and bare silicon SRAM. The MCM was used in the company's Delta line of ATE testers.-Responsible for design, development and management of the Memory system board used in high speed VLSI testers.