Audio Signal Processing Circuits for MEMS microphone

Design Proj 1: First Si success by meeting highly challenging specs for a 24-Ch LED controller Chip. As the Architect, and Chip as well as Analog Lead for the chip, designed Bandgap, Oscillator, ldo, biasgen, reference generator and precision V to I control high voltage output driver. Also designed the ESD scheme to achieve highly demanding ESD spec by the customer. Worked hand in hand with AE, TE and Marketing to take the development of the project from scratch to customer sampling… Show more Design Proj 1: First Si success by meeting highly challenging specs for a 24-Ch LED controller Chip. As the Architect, and Chip as well as Analog Lead for the chip, designed Bandgap, Oscillator, ldo, biasgen, reference generator and precision V to I control high voltage output driver. Also designed the ESD scheme to achieve highly demanding ESD spec by the customer. Worked hand in hand with AE, TE and Marketing to take the development of the project from scratch to customer sampling. Design Proj 2: Design 5 MHz Oscillator with +/- 1% precision and low power power on reset, also designed the analog top for a high speed control switch Show less

Designed very low power sub-1V bandgap, RC based oscialltor with Trim for precision control, and power on reset circuit with < 1 uA quiscent current

Design Proj –1: Led a feedforward based audio noise cancellation system Design Proj –3: Took ownership of few blocks of feedback based noise cancellation audio system and helped the team tape out the part on time. Simulated compensation Thomas-Tow Type Fourth Order Biquad filters over PVT, optimized parameters for process and voltage variation. Also design the soft switch for bypass mode. Simulated the talk-thru and bypass mode. Created the top-level, analog as well Chip top level, and… Show more Design Proj –1: Led a feedforward based audio noise cancellation system Design Proj –3: Took ownership of few blocks of feedback based noise cancellation audio system and helped the team tape out the part on time. Simulated compensation Thomas-Tow Type Fourth Order Biquad filters over PVT, optimized parameters for process and voltage variation. Also design the soft switch for bypass mode. Simulated the talk-thru and bypass mode. Created the top-level, analog as well Chip top level, and simulated thru Mixed signal AMS. Ran mixed signal verification thru regression test before the tape-out.Design Proj –4: Designed a divided by four (4) asynchronous counter, basic combinational logic blocks, flip flops in 0.18 um CMOS using CML logic. Show less

Design Proj-1: Design of a voltage mode LVDS driver with 3 dB and 6 dB pre-emphasis to be used in SDI cross point switch application Design Proj-2: Design Lead of 6.4-10 Gbps Equalizer for FR4 backplane Coordinated/led a 6.4-10 Gbps equalizer design project (DS64EV400L) in BiCMOS2 (2.5 V NPN and 2.5/1.8 V MOS) that works upto 40 inch 5 mil FR4 trace with less than 0.2 UI of total jitter. Highlight: demonstrated first Si success in delivering a product that is… Show more Design Proj-1: Design of a voltage mode LVDS driver with 3 dB and 6 dB pre-emphasis to be used in SDI cross point switch application Design Proj-2: Design Lead of 6.4-10 Gbps Equalizer for FR4 backplane Coordinated/led a 6.4-10 Gbps equalizer design project (DS64EV400L) in BiCMOS2 (2.5 V NPN and 2.5/1.8 V MOS) that works upto 40 inch 5 mil FR4 trace with less than 0.2 UI of total jitter. Highlight: demonstrated first Si success in delivering a product that is suitable upto 40 inch of FR4 with 0.2 UI of total jitter for PRBS7 and 10.Design Proj-3: Designed L-C tank VCOs with Center Frequencies of 6 and 10 GHz in NPN and NMOS BiCMOS operating at 2.5 V Role: Defined the package, Pin/PAD out, designed VCOs with center frequencies of 6 and 10 GHz using on-chip spiral inductance of 0.5 and 1 nH with 4 bit current DAC for amplitude tuning and 5 bit CAP DAC for frequency tuning, KVCO of 250 MHz/V Design Proj-4: Team Leader (jitter cleaner/clock systhesizer/clock distribution)Led a group of 5 designers in designing a PLL/VCO based jitter cleaner in 3.3 V BiCMOS process with random additive jitter spec about 30 fs,Design Proj-5: Block design: 1.8 V voltage regulator for 10/100 high Precision Phytero A 56 mA LDO at 1.8 designed to not require off-chip compensation capacitors. Design Proj-6: AGC (Automatic gain Control) and AEQ (Analog Equalizer) circuits modified to reduce offset due to cobalt stringer process issues. Show less

Design Proj-1: Designed of a combined Analog Gain Control (AGC) and AAEQ for 10/100 PHY in 0.18 um CMOS technology at 1.8 Vo In the early version of 10/100 phyter the Analog Gain Control and Analog Equalizer was two separate blocks using two operational amplifiers. In this design the operation of AGC and AEQ was consolidated in one block to reduce the power and the area. o The AGC is comprised of a 4 bit DAC to output an attenuation of -6 to -15 dB and AEQ was a 3 bit DAC with… Show more Design Proj-1: Designed of a combined Analog Gain Control (AGC) and AAEQ for 10/100 PHY in 0.18 um CMOS technology at 1.8 Vo In the early version of 10/100 phyter the Analog Gain Control and Analog Equalizer was two separate blocks using two operational amplifiers. In this design the operation of AGC and AEQ was consolidated in one block to reduce the power and the area. o The AGC is comprised of a 4 bit DAC to output an attenuation of -6 to -15 dB and AEQ was a 3 bit DAC with maximum gain of 20 dB at 62.5 MHz to equalize the inverse response of CAT 5 cable. AEQ was composed of a DAC and an operational amplifier. The linearity measured was 50 dB. Design Proj-8: A 7 bit 125 MHz Pipeline Analog to Digital Converter with Mid-sampling comparison for Gigabit PHY in 0.13 um 1.0V/2.5 V TSMC CMOS process. Designed a double-sampled pipeline analog-to-digital converter (ADC) in 0.13 um CMOS process at 2.5 V. It composed of serially coupled sample and hold circuit, 1.5 bit sub-ADC stages for residue, comparator and digital-to-analog conversion (DAC) circuitry and timing and control circuitry , 3 bit flash. Design Proj-9: Design a DLL In 2.5 V/1 V, 0.13 um CMOS processo A DLL designed to support 12 phases of a 8 ns clock each phase locked to the referennce clock . PVT Sims for V to I converter ran to ensure the delay within 4 to 12 ns so that the phase error can be corrected. DLL phase response, Frequency response, loop sims were run to ensure proper operation. Allso rigorous PSRR sims were run.Design Proj-10: A 1.8 V 4.2 mW Low power analog equalizer for Gigabit PHY with current mode digital to analog converter in 0.18 um CMOS o Designed a analog equalizer (AEQ) that provides maximum boost of 20 dB and compensates for signal attenuation In 125 m of CAT5 cable. The design Is Implemented In 0.18 um CMOS and uses 1.8 V supply. The power consumed by the AEQ Is only 4.2 mW. Measured linearity was 55 dB at 10 MHz Show less

As the lecturer in the department of Electrical and Electronic Engineering, took undergraduate courses on Electrical and Electronic Engineering