Achint Sharma Email and Phone Number
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Achint Sharma personal email
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Experienced Physical implementation Engineer with substantial knowledge base in Place & Route, Physical Verification, Low Power techniques & Signoff in technologies from 65nm, down to 3GAPAchivements:-- designed and implemented Adaptive voltage scaling for automotive GPU.- Implementing first ARM based MCU for automotive - Full chip P&R using Cadence Innovus.- Major Projects :-EyeQ3 ,TeseoIII ,Eiger, Velvety,Monaco- Good exposure to Safety critical designs targeted for automotive applications. - Analog-Digital mixed mode Back End flow using cadence(encounter)/synopsys(ICC) tools.- Experience of Handling analog block custom routing like Flash PMU,PLL,OSC and ADC's.- Experience of handling multi-power domain design.- Sound knowledge of IO ring generation considering current consumption , ESD protection and EWS rules.- Hands on experience on Physical verification using mentor's tool calibre.- Good knowledge of STA Specialties:-1- Mixed signal design floor planning 2- Fullchip/block level PnR.3- IO Ring generation 4- STA 5- Full chip Physical Verification
Synopsys Inc
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Senior Staff Application EngineerSynopsys Inc Feb 2023 - PresentSunnyvale, California, Us
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Staff Application EngineerSynopsys Inc Jun 2019 - Feb 2023Sunnyvale, California, Us
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Sr Application Enginner IiSynopsys Inc Jul 2018 - Jun 2019Sunnyvale, California, Us
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Staff EngineerStmicroelectronics Nov 2015 - Jul 2018Geneva, Switzerland, ChOwner of Full Chip implementation at 28FDSOI,chip having 11M instance count running at 500MZ -
Soc Technical LeaderStmicroelectronics Dec 2013 - Oct 2015Geneva, Switzerland, ChImplemented IORING ,Custom Routing floor planning ,CTS ,routing ,full chip physical verification.Successfully taped out 3 Automobile IC's at 40nm with an instance count varing from 1M to 5M.Major projects are TeseoIII which is a navigation devices,Eiger and velvety which are safety devices.Major challenges were congestion and power domains
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Sr. Design EngineerStmicroelectronics Feb 2012 - Dec 2013Geneva, Switzerland, ChWorked on block level netlist to GDSII ,as well as full chip IO ring creation and bump placement at 40nmImplemented 2 processors.Major projects were EyeQ3 which is an ADAS , Monaco which is a safety devices for automobile.... And few more.
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Design EngineerStmicroelectronics Mar 2011 - Jan 2012Geneva, Switzerland, ChWorked on full chip physical verification and ECO implementation.Understand the ST's unicad flow and did custom route for automobile IC.Read documents about the integration of Analog IP's on full chip.
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Design EngineerSmartplay Technologies Sep 2010 - Feb 2011Bangalore, Karnataka, InWorked on block level PnR activities on 28nm .Other than PnR I was responsible for Block level STA and physical verification . -
Asic Design EngineerUniquify Inc Feb 2009 - Aug 2010San Jose, Ca, UsExecuted block level netlist to GDSII Block is having an instance count varying from 700k to 1million on 65nm technology node.
Achint Sharma Skills
Achint Sharma Education Details
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International Institute Of Information Technology Hyderabad (Iiith)Microelectronics & Vlsi Design
Frequently Asked Questions about Achint Sharma
What company does Achint Sharma work for?
Achint Sharma works for Synopsys Inc
What is Achint Sharma's role at the current company?
Achint Sharma's current role is In the process of making transition smooth while juggling between cognitive thinking ,distortion & learning..
What is Achint Sharma's email address?
Achint Sharma's email address is achint.sharma@st.com
What schools did Achint Sharma attend?
Achint Sharma attended International Institute Of Information Technology Hyderabad (Iiith).
What are some of Achint Sharma's interests?
Achint Sharma has interest in Health, Science And Technology, Economic Empowerment.
What skills is Achint Sharma known for?
Achint Sharma has skills like Static Timing Analysis, Physical Design, Asic, Physical Verification, Timing Closure, Vlsi, Floorplanning, Soc, Eda, Verilog, Semiconductors, Tcl.
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