Adam Straw Email & Phone Number

Santa Clara, Ca, Us

Seattle, Washington, Us

Santa Clara, California, Us

● Accelerating deep learning workloads using MLIR on Intel hardware (CPU, GPU, VPU)● Developing an open source tensor compiler named PlaidML featuring a C++ domain specific language lowered through custom MLIR dialects and passes to generate code on Intel hardware● Completed proof-of-concept with PlaidML on Intel Gen9 graphics with good performance results compared with hand tuned libraries across several computer vision networks● Implemented fixes to the subgroup / tiling optimization pass cost model resulting in 20% performance improvement on Intel Gen9 / ResNet50● Evaluating baseline MLIR support for deep learning workloads and working to set Intel MLIR strategy

Santa Clara, California, Us

● Developing nGraph, an open source C++ based compiler from Intel which accelerates workloadsfrom deep learning frameworks such as TensorFlow on a variety of Intel hardware● Key contributor to nGraph core design and implementation: Deep learning graph constructionAPIs and operators, optimization passes and intermediate representation● Quantization lead: Developed a strategy to efficiently and accurately train and run quantizeddeep learning models with nGraph● Customer champion: Partnered with Microsoft and Waymo to build real-world solutions usingnGraph and Intel hardware● Worked across business organizations to promote and take the first steps toward a single APIfor AI compute at Intel forming the basis for OpenVino and nGraph merger● Created and chaired the nGraph Design Forum to ensure proper vetting and transparentcommunication of upcoming nGraph design changes● Architect for initiatives around programmability and debuggability of deep learning hardware aswell as user experience and MLIR● Product manager for nGraph; setting priorities for nGraph engineering team and establishing aroadmap for nGraph based on business partner needs and industry trends● Experience with deep learning frameworks such as TensorFlow, ONNX, and MXNet

Santa Clara, California, Us

● Created Maestro, ​a cross-platform C++ compiler based on LLVM and Clang special-purposed forvalidation of Intel products● Developed C++ object oriented software using Scrum / Agile process and industry standardtools such as Microsoft Visual Studio and Git● Led team training sessions and code dojos focused on teaching C++ best practices● Chaired the Maestro Architecture Forum which was responsible for driving all architecturalchanges for the tool● Fostered one-on-one / team meetings between individuals with disparate opinions to bring theMaestro team into better alignment● Drove cross-organizational effort to reduce validation costs by converging on a single solutionfor Intel Graphics validation using Maestro2● Partnered with customers to enable and optimize the Maestro graphics solution resulting inperformance and usability increases vs. previous generation tools● Eliminated 3-5 quarters development effort by reusing existing graphics test content withinMaestro● Co-authored a paper detailing Maestro graphics solution which was presented at an Intel-wideconference to further validation methodologies within the company● Mentored a peer to take over as Maestro graphics lead providing career growth for both partiesand reducing headcount investment

Santa Clara, California, Us

* Coordinated cross-organizational teams to take complex and broken hardware designs and deliver elegant and functional Intel products* Developed expert understanding of computer system architecture and Intel Core / Graphics micro-architecture* Created test plans, developed test content, debugged test failures and root caused numerous defects resulting in high quality Intel products* Mentored colleagues on validation tools and debug tactics during tour-of-duty in Oregon summer 2008* Reduced Intel Graphics test content by 43% and saved one quarter development effort with no coverage loss; influenced partner organizations to adopt these efficiencies* Authored two papers on Intel Core / Graphics validation best practices which were presented at an Intel-wide conference to further validation methodologies within the company* Improved execution efficiency and increased debug throughput in project level leadership roles

Bachelor Of Science (B.S.) With Distinction (Magna Cum Laude), Computer Engineering

Intro To Artificial Intelligence - Stanford Cs 271