Adam Wahl Email & Phone Number

Fort Collins, Colorado Area

Wrote Verilog testbench simulations verifying 16nm Mixed Signal subsystems that implement such IP as PLLs, converters, clock buffers, crystal oscillators, power management, ADCs and DACs.

Provided technology and library benchmark data. Created a reduced block design flow using various IP RTL ranging from ARM processors to networking IP with block size ranging from 35K to 115K gate count.Implemented frequency sweep and area utilization sweep experiments to compare metrics between multiple technology versions, libraries, and implementation methodologies measuring performance, power, area, DRCs, VT usage, and cell usage.Aided library design team with different architectural experiments using realistic block benchmarks as an early indicator of different topographical benefits/drawbacks.

Integration tested complex IP synchronicity releases to the design community such as DDR PHY, SERDES, ARM & PPC embedded processors and PCI-Express architecture blocks for verifying consistency across all deliverables, ensuring quality and examining the ability to integrate the IP within the context of a SoCCoordinated with Project Managers complex IP release schedules and BOM requirements confirming deliverables match that of the maturity level of the release.

Developed standard cell library and IO buffer models for Verilog simulation along with Logicvision scan models and pad libraries for boundary scan.

Characterized standard cell libraries, complex IO buffers and PLLs for timing and power using HSPICE-based SiliconSmart and modeled into Synopsys DB reference library format.