Adarsh Panikkar

Adarsh Panikkar Email and Phone Number

SOC integration | Interconnects @ Facebook
menlo park, california, united states
Adarsh Panikkar's Location
Greater Seattle Area, United States
Adarsh Panikkar's Contact Details

Adarsh Panikkar personal email

n/a

Adarsh Panikkar phone numbers

About Adarsh Panikkar

Extensive expertise in the full life-cycle silicon development of cutting edge processor and chipset high-speed interconnect ASICs, SOC integration. TECHNICAL SKILLSComputer architecture, ASIC design flow, Logic design, Low power, Custom CMOS, Design for testing/debug, Analog mixed signal verification, Synthesis, Timing closure, Formal equivalence, Clock Domain crossing, Post silicon validation, Board / tester debug, Oscilloscopes, BERT, PCI-E, AMBA.

Adarsh Panikkar's Current Company Details
Facebook

Facebook

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SOC integration | Interconnects
menlo park, california, united states
Website:
facebook.com
Employees:
77517
Adarsh Panikkar Work Experience Details
  • Facebook
    Soc Design Engineer
    Facebook Aug 2020 - Present
    Redmond, Washington, United States
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  • Qualcomm Cdma Technologies
    Engineer Iv
    Qualcomm Cdma Technologies Jan 2017 - Present
    Greater San Diego Area
    RF digital subsystem architecture and design.
  • Microvision Inc.
    Senior Staff Electrical Engineer
    Microvision Inc. Aug 2017 - Mar 2020
    Redmond, Washington
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  • Intel Corporation
    Senior Design Engineer
    Intel Corporation Aug 2011 - Aug 2016
    Dupont, Wa
    Responsible for architecting, implementing and debugging next generation memory and processor interconnect ASICs for Intel Xeon platforms; analyzed risk of critical business decisions; maintained documentation. Supported design integration, synthesis, STA, and lab bring up.
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  • Intel Corporation
    Component Design Engineer
    Intel Corporation Jun 2001 - Mar 2011
    Dupont, Wa
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  • Motorola
    Design Engineer | Personal Communications Sector
    Motorola Aug 1999 - Aug 2001
    Austin, Tx
    Responsible for design and verification of Wireless broadband digital ASICs
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  • The University Of Texas At El Paso
    Graduate Teaching/Research Assistant
    The University Of Texas At El Paso 1997 - 1999
    Developed an algorithm to partition designs on a time multiplexed FPGA.Teaching assistant for Computer Architecture
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Adarsh Panikkar Skills

Logic Design Low Power Design Verilog Soc Vlsi Rtl Design Asic Computer Architecture Fpga Logic Synthesis Pcie Systemverilog Functional Verification Static Timing Analysis Timing Closure Semiconductors Application Specific Integrated Circuits Modelsim Debugging Board/tester Oscilloscope Integrated Circuit Design Circuit Design C Cmos Mixed Signal Cadence Virtuoso Field Programmable Gate Arrays Very Large Scale Integration System On A Chip

Adarsh Panikkar Education Details

Frequently Asked Questions about Adarsh Panikkar

What company does Adarsh Panikkar work for?

Adarsh Panikkar works for Facebook

What is Adarsh Panikkar's role at the current company?

Adarsh Panikkar's current role is SOC integration | Interconnects.

What is Adarsh Panikkar's email address?

Adarsh Panikkar's email address is ap****@****ook.com

What is Adarsh Panikkar's direct phone number?

Adarsh Panikkar's direct phone number is +140876*****

What schools did Adarsh Panikkar attend?

Adarsh Panikkar attended The University Of Texas At El Paso, Manonmaniam Sundaranar University.

What are some of Adarsh Panikkar's interests?

Adarsh Panikkar has interest in Guitars, Economic Empowerment, Amps, Science And Technology, Ethnic Music Instruments, Human Rights, Animal Welfare, Instrumental Music Improvisation, Arts And Culture.

What skills is Adarsh Panikkar known for?

Adarsh Panikkar has skills like Logic Design, Low Power Design, Verilog, Soc, Vlsi, Rtl Design, Asic, Computer Architecture, Fpga, Logic Synthesis, Pcie, Systemverilog.

Who are Adarsh Panikkar's colleagues?

Adarsh Panikkar's colleagues are Damien Williams, Qoşqar Bahadurlu, Alex Nych, Martin Avila, Ballaj Fatima, Bret Hobbs, Sef Zad.

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