• Pixel design for Time-of-Flight (i-ToF and d-ToF), mobile, automotive, computer vision, and multispectral image sensors• Pixel design lead for IMX766, which has been adopted by more than 100 smartphone models on the market - the first Sony Semiconductor Solutions America design to achieve mass production (Design, optimization, DOE, characterization, analysis, correlation, debugging, feedback)• Successful prototype development of world’s first gated indirect time-of-flight (i-ToF) sensor with dual conversion gain for 3-dimensional imaging/depth-sensing camera (LCAD, TCAD, DOE, Process Input, Characterization, analysis, correlation, feedback); 5 patents pending at USPTO• Successful design and optimization of barrierless SPAD d-ToF sensor (LCAD, TCAD, DOE, Process Input, analysis, correlation, feedback); 1 patent pending at USPTO• Successful design and optimization of a 3.0µm-pixels and 1.5µm-pixels combined CMOS Image Sensor for Viewing and Sensing Applications with 106dB Dynamic Range, High-Sensitivity, LED-Flicker Mitigation and Motion Blur-reduction• Designed and optimized GS/RS RGB-IR sensor (Prototype)• Designed and optimized low power CMOS image sensor to support both viewing and sensing applications (Prototype)• LCAD and TCAD for 2-Layer Transistor Pixel stacked CMOS image sensor technology with a pixel structure that separates photodiodes and pixel transistors on different substrate layers• University Collaboration: Conducted technology scouting; Initiated discussions, fostered collaborations with professors, and drove project development• Patent coordinator for pixel, optics, and evaluation teams

• Developed and optimized etch recipes for 14nm, 10nm, 7nm, 5nm, and "beyond 5nm" technology nodes working in 300mm and 450mm cleanroom facilities; • 3 granted patents• Tools and Softwares used: Lam 2300 Flex, Kiyo, Versys Metal, and Titan (450mm) Reactive Ion Etch tools, NovaScan 3090 Next integrated metrology tool, AMAT CD SEM tool, Camtek Sela MC-600i cleave tool, Novellus Gamma 2130 tool, WaferViewer, SiView, LamDataAnalyzer, LamSpectraAnalyzer, Quartz PCI, Matlab, Semulator3D • Completed over 100 trainings including Plasma Physics & RF Delivery, 2300 Dielectric and Conductor Etch Process for Logic, Memory, and Productivity Applications, Etch Tools Hardware Overview, Fab Metrology, and EndPoint Detection. Fundamentals of PECVD, PEALD, Wet Etch and Clean Processes. FEOL Clean, BEOL Clean, Backside Etch, Bevel Cleans and Advanced Drying.

• Searching, Mapping, & Patentability Analysis: Performed 10 patentability searches using various databases viz. USPTO, Thompson Innovation, Google Patents, EPO, WIPO, Indian Patent Office, FPO, etc. and analyzed patentability with respect to prior arts.• Participated in invention understanding discussions with inventors; Prepared patent applications (Provisional and Complete); Drafted 8 patent specifications in accordance with the Indian Patent Office, European Patent Office, United States Patent and Trademark Office which met both firm and client's standards.• Proof read 3 patent applications for filing in Patent Offices.• Prepared prosecution responses addressing objections raised by patent examiners for 2 patent applications.• Prepared statements regarding working on commercial scale in India for 52 patented inventions to submit to the Indian Patent Office.• Worked on patent applications relating to a wide range of areas including software applications, communication networks/protocols, medical devices, robotic systems, Internet of Things (IoT)• Book Chapters: Contributed one complete chapter and a major portion of another chapter towards a book on Indian Patent System.• Conducted Historical Invention Study "The real inventor(s) of integrated circuits - Jack Kilby or/and Robert Noyce."• Knowledge of US, Indian, and European patent laws.

• Semiconductor Process, Device and Circuit Simulation, Modelling, and Optimization corresponding to MOSFET, BJT, Diodes, LDMOS, IGBT, and Superjunction devices• Simulation of semiconductor processes and devices through Sprocess, Tsuprem4, Medici, Sdevice, and other TCAD simulation platforms• Simulation of Circuits through HSPICE, NI-MULTISIM, TANNER tools, Xilinx, Medici, Sdevice, and other simulation platforms• Implementation of analytic models through software platforms such as MATLAB, MS-Excel, etc.• Process development and optimization for upcoming technology node of devices• Breakdown and characteristics analysis of transistors• Reliability studies such as HBM stress, TLP stress, and Unclamped Inductive Switching on MOSFETs and Power Devices

Tasks Performed:• TCAD simulations to optimize the new 0.15um Bipolar-CMOS-DMOS (BCD) technology. - Minimized Process Induced Stress stepwise - Eliminated 311 defects, dislocation loops and dislocation lines - Reduced leakage current - Improved yield• Kinetic Monte Carlo (kMC) simulations to optimize the implantation and diffusion (RTA) conditions for Arsenic implantation to reduce the extended defects and hence reduce the leakage current.• Calibration of UHV (800V) device characteristics• Optimization of Ron and BV by DOE/RSM• Improvement of PNP BJT beta• Debugging PNP BJT punch through effect