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Adarsh Basavalingappa Email & Phone Number

Principal Pixel Architect at Forza Silicon | PhD | Executive MBA at Forza Silicon
Location: Pasadena, California, United States 8 work roles 4 schools
1 work email found @sony.com 3 phones found area 518 LinkedIn matched
✓ Verified May 2026 4 data sources Profile completeness 100%

Contact Signals · 1 work email · 3 phones

Work email a****@sony.com
Direct phone (518) ***-****
LinkedIn Profile matched
3 free lookups remaining · No credit card
Current company
Role
Principal Pixel Architect at Forza Silicon | PhD | Executive MBA
Location
Pasadena, California, United States

Who is Adarsh Basavalingappa? Overview

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Quick answer

Adarsh Basavalingappa is listed as Principal Pixel Architect at Forza Silicon | PhD | Executive MBA at Forza Silicon, based in Pasadena, California, United States. AeroLeads shows a work email signal at sony.com, phone signal with area code 518, and a matched LinkedIn profile for Adarsh Basavalingappa.

Adarsh Basavalingappa previously worked as Principal Pixel Architect at Forza Silicon and Staff Pixel Design Engineer at Sony Electronics. Adarsh Basavalingappa holds Executive Mba from University Of Rochester - Simon Business School.

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Email format at Forza Silicon

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{first}.{last}@sony.com
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AeroLeads found 1 current-domain work email signal for Adarsh Basavalingappa. Compare company email patterns before reaching out.

Profile bio

About Adarsh Basavalingappa

Exceptional proven research expertise in areas of micro/nano-device design, fabrication, process development, optimization, and TCAD modeling and simulations in a multidisciplinary team environment. Research and Development of state-of-the-art CMOS, Image sensor, and BCD technology. Inventor/Co-inventor of 4 granted patents (5 pending), author/co-author of 6 journal articles, 13 conference proceedings, peer reviewed 25 submissions to reputable journals (IEEE sensors, IEEE T-DMR, JAP). Impactful professional evaluating university groups and establishing research projects relevant to the company.

Listed skills include Semiconductors, Matlab, Simulations, Nanotechnology, and 44 others.

Current workplace

Adarsh Basavalingappa's current company

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Forza Silicon
Forza Silicon
Principal Pixel Architect at Forza Silicon | PhD | Executive MBA
AeroLeads page
8 roles

Adarsh Basavalingappa work experience

A career timeline built from the work history available for this profile.

Principal Pixel Architect

Current

Pasadena, CA, US

Apr 2024 - Present

Staff Pixel Design Engineer

San Diego - US | Tokyo - JP, US

  • Pixel design for Time-of-Flight (i-ToF and d-ToF), mobile, automotive, computer vision, and multispectral image sensors
  • Pixel design lead for IMX766, which has been adopted by more than 100 smartphone models on the market - the first Sony Semiconductor Solutions America design to achieve mass production (Design, optimization, DOE.
  • Successful prototype development of world’s first gated indirect time-of-flight (i-ToF) sensor with dual conversion gain for 3-dimensional imaging/depth-sensing camera (LCAD, TCAD, DOE, Process Input, Characterization.
  • Successful design and optimization of barrierless SPAD d-ToF sensor (LCAD, TCAD, DOE, Process Input, analysis, correlation, feedback); 1 patent pending at USPTO
  • Successful design and optimization of a 3.0µm-pixels and 1.5µm-pixels combined CMOS Image Sensor for Viewing and Sensing Applications with 106dB Dynamic Range, High-Sensitivity, LED-Flicker Mitigation and Motion.
  • Designed and optimized GS/RS RGB-IR sensor (Prototype)
Oct 2020 - Apr 2024

Sr. Pixel Design Engineer

San Diego - US | Tokyo - JP, US

Oct 2017 - Oct 2020

Process Engineer Intern

Fremont, CA, US

  • Developed and optimized etch recipes for 14nm, 10nm, 7nm, 5nm, and "beyond 5nm" technology nodes working in 300mm and 450mm cleanroom facilities;
  • 3 granted patents
  • Tools and Softwares used: Lam 2300 Flex, Kiyo, Versys Metal, and Titan (450mm) Reactive Ion Etch tools, NovaScan 3090 Next integrated metrology tool, AMAT CD SEM tool, Camtek Sela MC-600i cleave tool, Novellus Gamma.
  • Completed over 100 trainings including Plasma Physics & RF Delivery, 2300 Dielectric and Conductor Etch Process for Logic, Memory, and Productivity Applications, Etch Tools Hardware Overview, Fab Metrology, and.
Aug 2014 - May 2017

Research Associate

New Delhi, Delhi, IN

  • Searching, Mapping, & Patentability Analysis: Performed 10 patentability searches using various databases viz. USPTO, Thompson Innovation, Google Patents, EPO, WIPO, Indian Patent Office, FPO, etc. and analyzed.
  • Participated in invention understanding discussions with inventors; Prepared patent applications (Provisional and Complete); Drafted 8 patent specifications in accordance with the Indian Patent Office, European Patent.
  • Proof read 3 patent applications for filing in Patent Offices.
  • Prepared prosecution responses addressing objections raised by patent examiners for 2 patent applications.
  • Prepared statements regarding working on commercial scale in India for 52 patented inventions to submit to the Indian Patent Office.
  • Worked on patent applications relating to a wide range of areas including software applications, communication networks/protocols, medical devices, robotic systems, Internet of Things (IoT)
Jun 2013 - Aug 2013

Graduate Research Assistant

霧峰區, 台中市, TW

  • Semiconductor Process, Device and Circuit Simulation, Modelling, and Optimization corresponding to MOSFET, BJT, Diodes, LDMOS, IGBT, and Superjunction devices
  • Simulation of semiconductor processes and devices through Sprocess, Tsuprem4, Medici, Sdevice, and other TCAD simulation platforms
  • Simulation of Circuits through HSPICE, NI-MULTISIM, TANNER tools, Xilinx, Medici, Sdevice, and other simulation platforms
  • Implementation of analytic models through software platforms such as MATLAB, MS-Excel, etc.
  • Process development and optimization for upcoming technology node of devices
  • Breakdown and characteristics analysis of transistors
Sep 2010 - Aug 2012

Device Simulation And Design Intern

Hsinchu, TW

  • Tasks Performed:
  • TCAD simulations to optimize the new 0.15um Bipolar-CMOS-DMOS (BCD) technology. - Minimized Process Induced Stress stepwise - Eliminated 311 defects, dislocation loops and dislocation lines - Reduced leakage current.
  • Kinetic Monte Carlo (kMC) simulations to optimize the implantation and diffusion (RTA) conditions for Arsenic implantation to reduce the extended defects and hence reduce the leakage current.
  • Calibration of UHV (800V) device characteristics
  • Optimization of Ron and BV by DOE/RSM
  • Improvement of PNP BJT beta
Jul 2011 - Sep 2011
4 education records

Adarsh Basavalingappa education

Executive Mba

University Of Rochester - Simon Business School

Doctor Of Philosophy (Ph.D.), Nanoscale Engineering

University At Albany

Master'S Degree, Semiconductor Technology (Dept. Of Computer Science & Information Engineering)

Asia University (Tw)

Bachelor'S Degree, Electronics And Communication (P E S Institute Of Technology)

Visvesvaraya Technological University
FAQ

Frequently asked questions about Adarsh Basavalingappa

Quick answers generated from the profile data available on this page.

What company does Adarsh Basavalingappa work for?

Adarsh Basavalingappa works for Forza Silicon.

What is Adarsh Basavalingappa's role at Forza Silicon?

Adarsh Basavalingappa is listed as Principal Pixel Architect at Forza Silicon | PhD | Executive MBA at Forza Silicon.

What is Adarsh Basavalingappa's email address?

AeroLeads has found 1 work email signal at @sony.com for Adarsh Basavalingappa at Forza Silicon.

What is Adarsh Basavalingappa's phone number?

AeroLeads has found 3 phone signal(s) with area code 518 for Adarsh Basavalingappa at Forza Silicon.

Where is Adarsh Basavalingappa based?

Adarsh Basavalingappa is based in Pasadena, California, United States while working with Forza Silicon.

What companies has Adarsh Basavalingappa worked for?

Adarsh Basavalingappa has worked for Forza Silicon, Sony Electronics, Lam Research, Lakshmikumaran And Sridharan, and Asia University (Tw).

How can I contact Adarsh Basavalingappa?

You can use AeroLeads to view verified contact signals for Adarsh Basavalingappa at Forza Silicon, including work email, phone, and LinkedIn data when available.

What schools did Adarsh Basavalingappa attend?

Adarsh Basavalingappa holds Executive Mba from University Of Rochester - Simon Business School.

What skills is Adarsh Basavalingappa known for?

Adarsh Basavalingappa is listed with skills including Semiconductors, Matlab, Simulations, Nanotechnology, C, Vlsi, Vhdl, and Verilog.

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