Projects included:• Generated new architecture for 2 Circuit Card Assemblies to be used in new generation Endoscopy Camera and Light Source. Designed a total of 6 PCBs in 6 months. • Electrical Engineer for the Endoscopy Light Source. Responsible to keep stakeholders informed as to schedule and generate recovery plans for items that fall behind schedule • Developed First Generation Test Protocols for DVI testing of current generation of imaging system used in the field. • Support all 60601 testing protocols used for the current system also incorporate the latest FDA requirements for design of Software and Firmware.

• Generated new architecture to replace the current one utilizing advanced technologies for the control system in the sensor pod resulting in major labor and material cost savings. Formulated cost & labor schedules to successfully implement this architecture. Delivered Proposal Memos and detailed documentation on the architecture for stakeholders and the customer. • Engineering lead for 6 FPGAs and 2 circuit card assemblies (CCAs). • Main Engineering POC for analysis of system issues discovered at customer site and to provide solutions and documentation to stakeholders for validation and verification. • Successfully managed a team of engineers involved in system Integration and Test of Sensor, also coordinated the updating effort with field engineers customer sites. • Electrical Engineering representative on a cross-disciplinary team involved in on-going site wide Engineering processes improvement, and to preparation for a CMMI Level 4 assessment.

• Designed and verified 3 FPGAS in the RADAR Scene Interface Unit sub-system of the RSG with clock speeds set to run at 200 MHz range.• Acted as interim Digital Hardware Lead on Aegis Radar Scene Generator (RSG) HIL tested system; lead on both sub-system and system level issues. Generated schedules and guided fellow engineers on the design effort. Generated trade studies used for determining technology choices for design enhancements. Interfaced with the customer and various stakeholders to determine future design requirements and improvements to RSG system.• Worked on EQ-36 Antenna Equipment FPGA. Redesigned FPGA code from a baseline design used in another program re-architected the CCA for different requirement of the EQ-36 system from the baseline system involving different FPGAs use of 1 gigE vs. 10 gigE interface.• Reconfigured and reused circuit card assembly (CCA) with several programmable logic devices to be used in the Multi-Mission Signal Processor (MMSP) program. Tested CCAs and integrated into the MMSP Radar test bed system at the customer site. • Configured and performed test of Mission Critical Enclosures (MCE) for several AEGIS baselines. Enclosures consist of Networking equipment, VME enclosures that contain both custom AEGIS modules and COTS modules, SAN devices. • Designed three circuit card assemblies with programmable logic to be used in the Multi-Mission Signal Processor Program.

Developed FPGA designs from concept and followed through to test & integrationDeveloped FPGA based VHDL designs targeting devices from Xilinx, Altera, Actel, QuickLogic and Orca FPGAs. The designs were used on following programs: THAAD, XBR, BMDS, SPY-3, ADSATCOM, GMSK Satcom, SMART-T, Trident, Aegis Standard Missile Blk IVA.

Developed software models for network protocols behavior on the Switching Network. Developed test plans and programs for PC and Macintosh systems using Secure Fast Packet Switching Technology. Protocols tests developed for include TCP/IP, IPX, and AppleTalk. Developed test plans and programs for PC and Macintosh systems using 3Coms Switching Technology called Switchblade. Protocols tests developed for include TCP/IP, IPX, and AppleTalk. Programming language used to test was TCL/TK.

Developed and taught full-custom CMOS Advanced VLSI Design and Fabrication courses. Sent several project chips for fabrication.Taught electronics, programming, lab and senior project classes. Integrated commercial tools from Viewlogic Software in ECE program. Worked with Actel and Xilinx FPGAs for courses.On different college-wide committees to: (1) decide on the use of computers in the Division of Arts & Sciences (2) salary & benefits (3) freshman retention.

Developed HIgh Speed ECL based logic fabric for next generation high speed computer