IC Assembly & Packaging, customer technical support.

I volunteered time facilitating scheduled meetings, seminars, training courses.Assisting others with resume writing, interviewing techniques and networking events.

• Develop and implement optical transceivers assembly flow and processes.• Provide design and manufacture input for Flex circuits design. Perform DFM, first article and prototype builds, FA and process improvements with Flex Circuit vendors and CMs domestic and foreign.

• Packaging development engineer for 2.5D/3D packaging projects using TSMC CoWos packaging.• Managing development and qualification of 2.5D/3D projects at OSATs• Interfacing with the IC Design teams to advise and direct IC and package layout requirements to meet wafer fab and assembly design rules.

A EDD funded and volunteer managed support center for professionals in employment transition.I volunteered time facilitating scheduled meetings, seminars, training courses, videographing and editing. While also availing of the many training courses offered at the center.

•Developed and qualified a stacked die CSP SIP module, using Film Die Attach, die thinning (100µm) and reverse wire bonding to enable ultra low profile modules for mobile GPS applications. •Developed and qualified a three die BGA CSP based GPS/Graphics processor employing side-by-side die and stacked memory die. Characterized and qualified Film Die Attach process to eliminate bleed and enable short length wire bonding.•Developed and successfully qualified two 45nm ELK devices, GPS/Graphics processor utilizing Cu pillar bump, Bump on Trace die attach, and Molded Underfill (MUF) in a CSP BGA package for both commerceal and automotive applications.•Review and approval of WLCSP and flip-chip RDL masks and stencils using AutoCAD, K-Layout and Cadence Allegro.•Optimized bond pad layout, wirebonding, and leadframe design using AutoCAD.•Completed Commercial and Automotive Reliability runs, including Board level Temp cycling and Drop Test per JEDEC test board requirements on 45nm, CSP packages for automotive applications.•Improved reliability of Automotive QFN devices, by employing selective spot plating to allow maximum Cu Leadframe Die Attach Pad (DAP) to mold compound adhesion area.•Developed next generation substrate and bump design rules: tightened die placement tolerance, improved the substrate lead etch process and optimized flux dip volume resulting in the elimination of die attach reflow shorts and opens at critical substrate locations. •Performed Root Cause Analysis on assembly and field failures, using combinations of continuity checking, X-Ray, X-Sectioning, Acoustic Microscopy, de-encapsulation, EDX, SEM, P-lapping.•Completed electromigration life validation testing of Cu-pillar bump design using Bond on Lead die attach to OSP coated bare Cu leads.

•Initiated flip-chip bumping process development projects with Taiwan engineering team. Received US Patent # 8759209 for an innovative re-passivation process. •Developed multi component MCM memory modules, containing wire bonded die, SOT23 ICs, surface mounted passive devices, crystal oscillators and status LEDs. •Invented a novel method of including a status indicator LED inside an over-molded MCM USB memory module and received a recognition award from SanDisk. •Drove the design and qualification of an 8 die laminate based 30mm LGA - dies were arranged in four 2-die stacks in a wirebond memory module.•Completed packaging characterizations of a MEM’s Variable RF Tuner for wireless devices.•Generated product roadmaps to ascertain current and future needs for flip-chip and WLCSP products. •Developed and qualified an exposed die back WLCSP on Leadframe QFN power management product for Volterra Inc., now a division of Maxim.•Developed a thick plated Cu RDL process option for power management WLCSP device, enabling lower IR losses and better load balancing among power switching cells.•Initiated projects to create and qualify the first Pb-Free and Cu-pillar bumped wafers at Statschippac, leading to successful release and enabling subsequent development of the molded under-fill option for flip-chip packages.•Established design rules for Cu-pillar bumping from 150 to 100µm, enabling higher density I/O routing, enabling two pass through signals on a 150µm bump pitch.•Wrote training material on electromigration and trained design center personnel on electromigration.

Manufacturing Process Engineer, developed and implemented manufacturing processes and tooling for Optical Packaging of Diode Pump Lasers for the Telecom industry.

Assembly and Process Development Eng. leading a production group in the assembly of Gold Bumped ICs to TAB/Flex Tape, COT, employing Thermo-Compression and Ultra-Sonic bonding.Implemented Dam and Fill encapsulation