Adrian Macias Email & Phone Number

Santa Clara, California, Us

Defining, developing, marketing, and enablement for AMD Pervasive AI customers and markets.

Mountain View, California, Us

Built and led a team of ML Solution Architects to drive customer enablement for Groq's technology.

Santa Clara, California, Us

As Product Planning Manager for Intel's FPGA Software Solutions, I led high performance teams to enable FPGAs as compute devices for developers in areas such as machine learning and other workload acceleration.- FPGA Machine Learning Solutions- High Level Design Software Compilers- OpenCL, High Level Synthesis, DSP Builder- FPGA Acceleration Solutions

Santa Clara, California, Us

Intel Programmable Solutions Group (formerly Altera Corporation).Technology Specialist FAE.Supporting: Compute & Storage, Cloud Service Providers, Data Center, Autonomous Driving, Broadcast Video, Military, Industrial, Wireless Comms, Medical, & Consumer.Specialties: Machine Learning, Compute Algorithms, Signal Processing, FPGA, OpenCL, High Level Synthesis, Mathworks, Simulink, DSP Builder, Verification.

Us

Marketing & Engineering Roles for Ultra Wideband chipset startup company.Working with the Technical Marketing team, I was responsible for developing application solutions using our ASIC chipset. Examples are Wireless-HDMI video streaming and Ethernet-over-Coax home networking solutions.Areas of development include authentication, content protection, streaming transports/formats and quality of service.I served as a standards group liaison and served as the technical interface to Tier 1 customer accounts and strategic channel partners. I was also credited with obtaining Digital Content Protection (DCP LLC) approval for our video solutions.Team lead for the baseband modem design.Spearheaded the verification test bench platform and developed overall chip architecture. Formalized all system integration and characterization activities and was promoted to System Integration Manager before joining the Technical Marketing team to drive product planning.

Ground floor employee to a wireless start-up company developing Ultra Wideband ASIC chipset, capable of transmitting over 114Mbps, a major leap in wireless communications at the time. Senior ASIC Designer responsible for signal processing and design implementation of digital baseband algorithms.Promoted into the System Engineering team, responsible for system ASIC design, architecture and platform integration, including RF, digital, and software sub-systems.Also served as technical resource to end-customers, assisting the integration into next-generation wireless audio-video consumer products and positioning next generation products.

Through my work with the Actel Rad Tolerant devices, I was recruited by the FPGA company to work as a field consultant for Tier 1 military, aerospace and commercial telecom companies who required the maximum performance advantage of the Actel FPGA devices.

Greenbelt, Md, Us

Converted from student internship working on software for Cassini mission to Saturn. Developed drivers and user interfaces for PCI bus devices used in Space Shuttle Ground Stations.Promoted to full-time Hardware FPGA engineer working on Radiation Tolerant designs for the Space Flight Electronics Group within the Small Explorers (SMEX) program. Also involved in radiation effects testing and responsible for trail-blazing next generation space flight bus architectures.

Msee, Signal Processing

Bsee, Communications & Signal Processing