Andrea Fantini Email & Phone Number

Leuven, Flanders, Be

Leuven

Leuven

Leading scientist in charge of the development and physical understanding of OxRRAM (RRAM) technology for embedded application. Coordinating the development, processing, characterization and modeling activity within a team of experts and PhD students.Main field of activity:- Embedded NVM for IoT, MCU - Radiation Hardening- Secure Applications

Leuven

Research Scientist in Memory Device Design Group (MDD) Conducting research in collaboration with IMEC's sub-10nm industrial partners on the technological development and physical understanding of emerging ultra-scaled memory technologies. Including with different extent:o Bipolar Oxide-based based ReRAMo Cu based CBRAMo Carbon Nanotube (CNT) memoryMain roles:- Physical and Compact Modeling, Design of Experiments- Evaluating performance and reliability properties of different materials / integration routes- Reporting to imec internal and external customers- Following collaboration with universityTutoring of Ph D / M. Sc / Internship students. Contributing (Authored or coauthored) to publications at top conferences (VLSI, IEDM, IMW) and journals (EDL, TED)

Grenoble Area, France

Researcher in the field of emerging Non-Volatile memories for embedded application. Strongly contributed to the start of Emerging Memory activities @ LETI (LTMA)(o) Developed Fast-Pulse ATE test system and test method (o) Developed Electrical test-setups for material analysis(o) Directed characterization and modeling activity for- Phase Change (PCRAM) NVM Memory (doped GeTe/GST)- Unipolar Oxide Resistive RAM (Pt/HfO/Pt, Pt/NiO/Pt)In the same context he led- process monitoring/improvement for device performance - reliability assessment for stringent embedded automotive specsTutored M.Sc and PhD students in the same research fieldAuthored or coauthored publications at top conferences (IEDM, IMW) and journals (EDL)

Milan Area, Italy

Scientist position in the field of Memory Architecture/Design in collaboration with NumonyxArchitectural evaluation and design of “Read Path” for MLC Phase Change Memory. • Feasibility study of non-linear sensing schemes for MLC PCRAM • Development of Positive-Feedback biasing scheme for access time minimization • Statistical characterization of temperature effects on 4 Mbit-180nm PCRAM Array• Tutoring Master/PhD students

Milan Area, Italy

PhD activity in the field of Memory Circuit Design in contact with Industrial partner (Numonyx) Design and evaluation of analog block for embedded and standalone non volatile memory chips.• Design of Sense circuitry for 128 Mbit PCRAM demonstrator• Design of Analog reference/biasing circuitry for 128 Mbit PCRAM demonstrator• Desing and evaluation of Write ciruitry, Charge pumps • Architectural evaluation of memory organization strategies

Pavia Area, Italy

Design and layout of Low-power, Low-Voltage (sub 1 V) Bandgap voltage reference for 130nm CMOS technology.

Ph.D., Microelectronics, Physics

Activities and Societies: Semiconductor, IEEE Student Branch, Associazione Dottorandi PavesiPh.D. Course on: "Electronic, Eletric.

Bachelor + M.Sc.;, Engineering

Activities and Societies: Microelectronics, IEEE Student BranchThesis Title: "Low Voltage, Low Power Bandgap reference for Phase Change.