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Arnab G. Email & Phone Number
Senior Program Manager
at
TSMC
1 work email found
@intel.com
2 phones found area 408
LinkedIn matched
✓ Verified May 2026
4 data sources
Profile completeness 100%
Current company
Role
Senior Program Manager
Location
Chandler, Arizona, United States
Company size
Who is Arnab G.? Overview
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Quick answer
Arnab G. is listed as Senior Program Manager at TSMC, a company with 23504 employees, based in Chandler, Arizona, United States. AeroLeads shows a work email signal at intel.com, phone signal with area code 408, and a matched LinkedIn profile for Arnab G..
Arnab G. previously worked as Engineering Manager; Director, Intel Foundry Accelerator - Design Services Alliance at Intel Corporation and Program Manager Technical at Intel Corporation. Arnab G. holds Ms, Computer Engineering from University Of Idaho.
Company email context
Email format at TSMC
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*@intel.com
68% confidence
AeroLeads found 1 current-domain work email signal for Arnab G.. Compare company email patterns before reaching out.
Profile bio
About Arnab G.
Management Skills:- Lead a geo-diverse team for 3+ years, establishing the Design Services Alliance for Intel Foundry Accelerator.- 4+ years of strategic sourcing experience in Design Services domain as a Global Strategic Supply Chain Manager, driving cost, quality, and efficiency improvements.- 5+ years of cross-functional program management, driving technical issue resolution and collaboration to meet aggressive product schedules.- Delivered on high-level milestones in fast-paced, leading node technology design and solutions engineering.- Managed issue resolution within diverse global teams, using data-based decision making.- Managed EDA vendor engagement across multiple technology nodes, handling business and technical aspects.Technical Skills:- 11+ years of experience in Digital Circuit Physical/Backend Design Flow development & implementation using Intel, TSMC, and NEC technologies.- Expertise in custom place and route, bump placement, RDL routing, floorplanning, partitioning, pin assignment, power planning, clock tree synthesis, RC extraction, ECO flow implementation, and full chip integration.- Experience with multi-million gate SoCs, high-speed DDR PHY IPs, ASICs, Structured ASICs, and Gate Arrays.
Listed skills include Soc, Asic, Static Timing Analysis, Physical Design, and 18 others.
Current workplace
Arnab G.'s current company
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Tsmc
10 roles
Arnab G. work experience
A career timeline built from the work history available for this profile.
Engineering Manager; Director, Intel Foundry Accelerator - Design Services Alliance
Current
Aug 2021 - Present
Program Manager Technical
Nov 2017 - Jul 2021
Foundry Program Manager
Oct 2014 - Nov 2017
Component Design Engineer
Feb 2011 - Sep 2014
Engineer, Principal - Ic Design; Engineer, Senior Staff - Ic Design
Chip Leadership: Independently managed the layout execution from gate level netlist to GDSII generation and release to fab for multi-million gate designs, overseeing both chip top and block levels.Physical Design and IP Management: Executed physical design and provided support for design guidelines and IP integration for 65nm and 40nm DDR PHY.
Aug 2007 - Feb 2011
Senior Design Engineer, Custom Soc Solutions
Design Execution and Project Management lead for backend design flow (RTL/Gate Level netlist to GDSII) – design processing and debug, discussion with customers and factory for establishment of project execution schedule, providing technical support to customers in NEC ASIC/Structured ASIC/Gate Array products, initializing and closely co-ordinating.
May 2004 - Jul 2007
Design Engineer, Custom Soc Solutions
Engineering team member for backend design flow execution (RTL/Gate Level netlist to GDSII) design processing and debug, providing technical support to customers in NEC ASIC/Structured ASIC/Gate Array products and release of completed design database for manufacturing.Pre-sales technical support for design evaluation.
May 2001 - Apr 2004
Asic Design Engineer, Strategic Chipset Development
ASIC Design Contribution: Engaged in the design and development of advanced multi-million gate ASICs for Compaq's cutting-edge servers.Module Development Oversight: Led the creation of module specifications, logic design, testbench, simulation, verification, and integration within ASICs.Collaborative Debugging and Integration: Partnered with peers and.
Jul 2000 - May 2001
Intern Engineer, R&D Cad Simulation Group
Evaluate circuit Simulation tools for netlist extraction & circuit simulation to help define, implement, automate and support engineering efforts in DRAM & SRAM circuit design.
May 1999 - Jul 1999
Team & coworkers
Colleagues at TSMC
Other employees you can reach at tsmc.com. View company contacts for 23504 employees →
PL
Pq Liao
Colleague at Tsmc
Hsinchu City, Taiwan, Taiwan, Taiwan, Province Of China
View →
MC
Meng-Ku Chi
Colleague at Tsmc
Taiwan, Taiwan, Province Of China
View →
葉
葉聖祺
Colleague at Tsmc
Hsinchu City, Taiwan, Taiwan, Taiwan, Province Of China
View →
HC
Han Chen
Colleague at Tsmc
Taiwan, Taiwan, Province Of China
View →
蔡
蔡瑞芳
Colleague at Tsmc
Taichung City, Taichung City, Taiwan, Taiwan, Province Of China
View →
RH
Raymond Hung
Colleague at Tsmc
Taichung City, Taichung City, Taiwan, Taiwan, Province Of China
View →
BY
Bryan Yu-Heng Chen
Colleague at Tsmc
Taiwan, Taiwan, Province Of China
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CY
Chien-Hao Yang
Colleague at Tsmc
Taiwan, Taiwan, Province Of China
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YZ
Yuhang Zhu
Colleague at Tsmc
New York, New York, United States, United States
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YC
Yuan Chiu
Colleague at Tsmc
Taipei–Keelung Metropolitan Area, Taiwan, Province Of China
View →
Pq Liao
Colleague at Tsmc
Hsinchu City, Taiwan, Taiwan, Taiwan, Province Of China
View →
MC
Meng-Ku Chi
Colleague at Tsmc
Taiwan, Taiwan, Province Of China
View →
葉
葉聖祺
Colleague at Tsmc
Hsinchu City, Taiwan, Taiwan, Taiwan, Province Of China
View →
HC
Han Chen
Colleague at Tsmc
Taiwan, Taiwan, Province Of China
View →
蔡
蔡瑞芳
Colleague at Tsmc
Taichung City, Taichung City, Taiwan, Taiwan, Province Of China
View →
RH
Raymond Hung
Colleague at Tsmc
Taichung City, Taichung City, Taiwan, Taiwan, Province Of China
View →
BY
Bryan Yu-Heng Chen
Colleague at Tsmc
Taiwan, Taiwan, Province Of China
View →
CY
Chien-Hao Yang
Colleague at Tsmc
Taiwan, Taiwan, Province Of China
View →
YZ
Yuhang Zhu
Colleague at Tsmc
New York, New York, United States, United States
View →
YC
Yuan Chiu
Colleague at Tsmc
Taipei–Keelung Metropolitan Area, Taiwan, Province Of China
View →
4 education records
Arnab G. education
Ms, Computer Engineering
University Of Idaho
Pgdba, Management/Business Administration
Icfai Business School, Mumbai
Cfa, Finance
Institute Of Chartered Financial Analysts Of India, Hyderabad
B.Sc. (Engineering), Electrical Engineering
Regional Institute Of Technology, Jamshepur (Now N.I.T., Jamshedpur)
FAQ
Frequently asked questions about Arnab G.
Quick answers generated from the profile data available on this page.
What company does Arnab G. work for?
Arnab G. works for TSMC.
What is Arnab G.'s role at TSMC?
Arnab G. is listed as Senior Program Manager at TSMC.
What is Arnab G.'s email address?
AeroLeads has found 1 work email signal at @intel.com for Arnab G. at TSMC.
What is Arnab G.'s phone number?
AeroLeads has found 2 phone signal(s) with area code 408 for Arnab G. at TSMC.
Where is Arnab G. based?
Arnab G. is based in Chandler, Arizona, United States while working with TSMC.
What companies has Arnab G. worked for?
Arnab G. has worked for Tsmc, Intel Corporation, Broadcom Corporation, Nec Electronics America, Inc., and Compaq Computer Corporation.
Who are Arnab G.'s colleagues at TSMC?
Arnab G.'s colleagues at TSMC include Pq Liao, Meng-Ku Chi, 葉聖祺, Han Chen, and 蔡瑞芳.
How can I contact Arnab G.?
You can use AeroLeads to view verified contact signals for Arnab G. at TSMC, including work email, phone, and LinkedIn data when available.
What schools did Arnab G. attend?
Arnab G. holds Ms, Computer Engineering from University Of Idaho.
What skills is Arnab G. known for?
Arnab G. is listed with skills including Soc, Asic, Static Timing Analysis, Physical Design, Eda, Integrated Circuit Design, Logic Design, and Debugging.
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