Anuj Agrawal Email & Phone Number

San Francisco, California, Us

San Francisco, California, Us

Key expertise demonstrated:Technical Leadership, Scrum Master, Defining FPGA Firmware architecture1. Collaborated cross-functionally for FW architecture definition & led design team across US & India to implement it on next revision of existing Velodyne ToF based LiDAR sensors to reduce manufacturing cost, enhance robustness and meet supply chain challenges

Key expertise demonstrated: Altera and Xilinx FPGA tools, FPGA firmware architecture, IP micro-architecture definition, RTL design, Test bench development, IP functional validation, Timing closure, Project Management1. Experienced on ToF Lidar Architecture. Designed, validated & created micro-architecture for various Lidar’s building blocks IPs implemented on FPGA/SoC: - Motor Control PID, Digital PLLs, Laser Return Processing, Intra-lidar communication & Image Quality Improvements2. Designed Digital Motor Encoder PLL IP to achieve azimuth precision of 0.01deg & jitter of less than 0.05deg 3. Contributed to implementation of IEEE-1588 (PTP) functionality and High-Speed Serial Communication for Automotive applications

1. Technical Lead - For Stratix10 FPGA F-Tile rollout. Responsibilities include: - Executing Go-To-Market (GTM) plan, planning team deliverables & prepare team for technical product support2. Technical lead – Ethernet IPs: - Developed, Productized & Scaled the tool – ‘Ethernet Link Inspector’ (patent pending - us 16/020,671)Soft Protocol Analyzer introducing ~20x efficiency for monitoring and debug of Ethernet Links - Responsible to develop team expertise for supporting various Ethernet IPs within FPGA with NRZ and PAM4 IO standard - Driving root-causes analysis efforts of hardware failures through lab experimentation and resolving system and board issues related to signal integrity with successful cross-functional collaboration3. Worked on implementation of industry’s next hot technology: Ethernet 1588 (Precision Time Protocol) and Flex-E (Ethernet)4. Design customer experience for Intel FPGA Ethernet IPs for higher customer satisfaction score5. Design best-in-class product demos displaying HSIO performance in various global conferences

1. Technical Manager for key customer accounts: - Technical adviser for system design using Intel FPGAs & capitalizing customer opportunities to design wins2. Tested and characterized SerDes PHY Deterministic Latency solution to be use by protocols like CPRI & RapidIO 3. Re-structured a methodical approach for teams to gain strong technical foundation in respective subject matter4. Supported Intel FPGA Ethernet IP Portfolio: 10G/25G/40G/50G/100GBase-R/CR/KR etc. 5. Contributed towards competitive analysis of FPGA Fabric Performance to influence planning of future Intel FPGAs6. Transformed customer facing collaterals (static & dynamic) for ease of use and enhanced experience

1. Responsible for post-silicon char & test for high speed SerDes TX and RX capabilities2. Automated SerDes I/O testing methodologies for efficient issue diagnosis and resolution3. Advocated customers on technical queries related to SerDes PHY Layer - Includes customer visits for debug and resolution of key issues4. Audited SerDes PHY re-timers & gearboxes from various vendors to evaluate the best fit for Intel requirement

San Jose, Ca, Us

- ISA for course Advanced Digital System Design and Synthesis.- Responsible to help students in their lab assignments and technical queries.

Palo Alto, California, Us

- Testing SoC’s for its failures and further Diagnosis to find the probable failing suspects.- Tracing Layout & Schematic to find the co-ordinates & associated logic of the failing suspect.- Developed Tcl/Tk GUI to analyze the failure logs & database to display the detailed info of the failing suspect.- Developed Tcl scripts for various Database Handling issues.

San Jose, Ca, Us

- ISA for course High Speed CMOS Design.- Responsible to help students in their lab assignments and technical queries.

Hinjawadi, Pune, Maharashtra, In

Worked as Graduate Engineer Trainee in Embedded System Group.

Master Of Science (M.S.), Digital Ic Design

Bachelor Of Engineering (B.E.), Electrical, Electronics And Communications Engineering