Technical manager in DSP-RTL area, architecture design, system level integration and verification of complete coherent DSP.In charge of toplevel integration, verification and bring-up for coherent optical transceiver chip.Customer IP integration and verification

Design and implementation of DSP algorithms for coherent optical transceivers. System level integration and fine tuning.Power reduction in micro-architecture design using algorithm optimization and digital implementation techniques.Optical transceiver chip bring-up, verification and calibration in optical laboratories at Inphi US offices in Irvine and Santa Clara.

Development, implementation and verification of DSP algorithmsfor high performance coherent optical transceivers.Specialization in chromatic dispersion compensation, channel equalization, adaptive filtering, multirate digital signal processing, high speed low power FFTs and carrier/timing recovery loops.Design of digital micro-architectures for DSP blocks.Experience in digital clocking, clock domain crossings, finite state machines, static timing analysis, fixed point arithmetic, design for testing.Verification at systems level, RTL level and gate level.Responsible for code coverage, code lint, gate level synthesis and technical documentation.Power estimation using several tools including Cadence suite.Task automation using python and bash.

Digital implementation and verification of LDPC error correcting codes in FPGA for satellite transceiver. Implementation in FPGA of micro-controller system using a soft microprocessor.

Development of image processing software to automatically measure wool fibres under digital microscope. Deploying custom Linux kernel in embedded Intel computer.