As an RTL Design and Validation Engineer with over 4 years of experience in the semiconductor field, I have played a key role in the success of critical software projects. My expertise in EDA tool validation and automation has driven significant improvements in efficiency and accuracy, ensuring the reliability and performance of complex FPGA designs.I specialize in RTL design, formal verification, and UVM methodologies, leveraging a deep understanding of various EDA tools, including Modelsim, Quartus Prime, and Synopsys Design Compiler. My work involves automating validation flows, conducting thorough verifications, and developing parsers for detailed log file analysis. These efforts have contributed to the optimization of design processes and the achievement of high-quality benchmarks.My collaborative approach and leadership skills have enabled me to work effectively with diverse teams, both locally and offshore, fostering a productive and inclusive environment. I am committed to continuous learning and innovation, always seeking to employ the latest methodologies and best practices in my projects.I am passionate about advancing the field of EDA and contributing to open-source projects. My goal is to leverage my technical expertise and leadership capabilities to drive technological advancements and deliver impactful solutions in the semiconductor industry.