Managing validation programs for Devices and client market segments across geographically diverse sites within Intel.1. One voice responsible for all Electrical (EV) & Functional Validation (FV) Execution to Product Mission Control. 2. PVT coverage Tools for all Analog Electrical Validation teams. Achieved 20% efficiency, actionable communication to executive management, and on-schedule completion of validation execution by developing silicon Process coverage tool for all Validation teams by collaborating with SOC circuit design, ATE manufacturing, and validation execution stakeholders for definition of all in-die variation tokens on client CPU programs for all interfaces. Devised & Maintained process coverage tools for skew silicon by maintaining silicon demand Vs inventory on cross-geo sites. Cherry-picked extreme process corner units from Plan of Record lots using their tools when skew material was not available or delayed. Generation of silicon process coverage metrics achieved by analog teams. 3. Drove validation execution team of 20+ engineers in dynamic cross-sites by diligently evaluating and communicating program status, bugs/sightings, and challenges to executive management and program leadership with weekly reports for Post silicon validation execution or pre-silicon readiness progress extracted from Power-BI dashboards, Key messages on Highlights/Lowlight and Risks with mitigation, and a summary of major showstopper sightings with clearly articulated next steps or help needed. 4. Improved product quality and reduced risk of recall by devising and conducting validation quality reviews across all sub-disciplines using companywide accepted Hardware Quality Release Criteria (HWQRC) scoring metrics across all PVT vectors for every PLC deliverable milestone.5.

Planning, resourcing, and executing complex cross-site DFx design and validation projects.1. Delivered 25% headcount cost savings for memory software/firmware teams delivering (planning, design, validation & integration) of Intel's first converged Memory Built-in Self-Test IP for Client and server CPU's. Lead a team of 12+ cross-site engineers to execute the development/convergence of this memory test Soft-IP from its cradle (TR) to release (IP integration) by planning detailed project design plans, hiring/recruiting staff, and driving execution of RTL development and validation collateral.2. Created detailed project execution plans, hired/recruited staff, and drove the execution of RTL development and validation collateral. 3. Communicated project milestones, roadblocks (with solutions), deliverables, dependencies, and status to a broad set of internal and external stake teams.4. Lead a team of 12 engineers in a daily debug dungeon to root cause and break down complex problems, remove bottlenecks, and assigning/tracking ownership of tasks. MBIST IP was delivered and integrated into the CPU design without adding any additional headcount burden. 5. Cluster Validation of High-Speed Serial I/O Margining method using I/O DFx on Intel SOC products. Reduced 2-3 weeks of debug and execution time for analog validation teams working on high-speed serial I/O's by leading a team of 4 engineers validating the synthetic Eye-height & Eye-width margining methods in pre-silicon simulation. TR (Tech Readiness) engagement with micro architects for the definition of DFx in PHY Hard-IP (HIP) and Soft-IP (SIP) Controller Roadmaps supporting PCIe, USB3, and SATA in chipsets and SOC products. Created detailed project execution plans and recruited engineers to drive the RTL validation effort. Wrote test cases and debugged RTL personally when short on staff.8. Wrote test cases and debugged RTL

Project Management, FPGA design, RTL validation and PCB Board design.Project: Xeon Server EV DFx Validation1. Wrote cluster level test cases to validate RTL for EV DFx in a test chip for Xeon server CPU. Project: Xeon Server CPU High speed Sideband signal capture device1. Wrote RTL for capturing high speed (DDR type) sideband signaling from Intel’s first multi-core architecture CPU. The design was implemented in Altera Stratix2 fpga. Project: Audio/Video Output capture FPGA for Intel’s Digital Home Audio/Video silicon validation platforms1. Developed specification and RTL code for the High/Standard definition audio/video output (AVO) capture FPGA to validate set-top box chip designs from Intel. Designed all video capture FUBs (functional unit blocks) attached to 1GB DDR DIMM, a pixel by pixel comparison/validation unit, and stream the captured video over a standards (SMPTE 292 & SMPTE 374) based pair of high speed serial cables to video display/capture equipment.2. Architected the common internal logic blocks and chassis bus architecture to provide DDR SDRAM (200 Mhz) access to all FUBs on AVO and AVI FPGA’s on the board. Developed Verilog BFM’s, test-benches, and test cases to simulate all the FUB’s at the unit and system level. All modules designed in Verilog using Altera Stratix GX device technology. 3. Proto-typed a standard definition to high definition mapping concept over dual SMPTE-374 high speed serial links, using fpga vendor provided evaluation board, before getting actual hardware in the lab. Designed a moving color bar generator for the evaluation fpga to generate various standard definition (NTSC 480i, PAL 576i), progressive (480p and 576p), and high definition (720p and 1080i) sources.

FPGA design, RTL validation and PCB Board design/test/debug Project: 10G Ethernet Service Module for Ciena CN4300 Metro Ethernet Switch1. Worked on the schematics for a 10G Ethernet service module, to provide a DWDM OTU-2 network interface. The PowerPC based CPU complex and the optics were pluggable cards onto the baseboard to constitute an assembled module.2. Designed the front-end data path FPGA to translate the XAUI interface on the network processor to the SFI-4 phase-1 interface on FEC chip, terminate a processor local bus, and a secondary XAUI interface to a LAN XFP optical module via a 10G SERDES PHY chip. Design done in VHDL. Project: Design of Cell based Switch Fabric Module for Ciena CN4300 Metro Ethernet Switch1. Designed, simulated and verified the controller FPGA with a full duplex proprietary link, a Compact Flash interface, and an interface between the CPU local bus and the processor interface on the fabric chip. Wrote the hardware/software interface specification document for this switch fabric module.2. Worked in the lab to debug, verify and fine-tune the 3.125 Gbps XAUI ultra high-speed backplane interface on the fabric module. Also published the DVT report for the recently designed 10 port 1GE service module that together with this fabric module completes an 80 Gbps layer-2 switching system.

Senior Hardware Design EngineerProject: Board Architecture and FPGA design of OC192c Line Card module for a Multi-Service MPLS Switch1. Worked with a team of senior hardware and software architects to define the architecture of the Packet thread processing module.2. Design of Egress Packet Re-assembly/Traffic Management FPGA with four OC48c interfaces from the switch-fabric and a single OC192c (POSPHY L4) interface to the network processor. 3. Drove board level design effort including, schematic capture and interfacing with a cross functional engineering services team/stakeholders of board layout designers, power supply engineers, diagnostic engineers, regulatory/compliance engineers, mechanical engineers, thermal engineers, software engineers, manufacturing engineers.Project: Board and FPGA design for a SONET OC48c PHY Module1. Design and verification of control FPGA in Verilog.2. Board level design including schematic capture and PCB layout specification, and signal integrity simulations.3. Authored Hardware verification & Results Report.4. Wrote diagnostic scripts to configure the chipsets (framers, serializers, optical modules etc.) for various traffic flows in the data path for prototype verification. Performed “Eye” pattern Compliance verification for the optics.Project: Gigabit Ethernet I/O board & FPGA design1. Designed the interface between the (basic input/output frame card) card and the MAC layer device on the PHY card using FPGA. This design was implemented in verilog with two internal dual clock FIFOs for the crossing of clock domains and de-coupling of two different interfaces. Supervised technicians for schematic capture and layout efforts while performing signal integrity simulations.2. Authored Hardware verification & Results specification document based verification in lab using logic analyzers, traffic generators, and digital scopes. Performed “Eye” pattern signal integrity verification for the optics using HP high-speed scope.

FPGA design, RTL validation and PCB Board design/debugProject: Design of GDC’s next generation Enhanced ATM Cell Controller.1. Designed and debugged interfacing logic for a cell extraction/insertion interface to the SAR processor, based on 1995 ATM Forum UTOPIA Level II protocol. The designs were done in VHDL, using Lattice and Altera devices. 2. Ran board level signal integrity simulations and analysis and drove the board place and route process, to optimize the signal integrity and static timing on the board. Project: Cost reduction and feature upgrades of APEX ATM Cell Controller Cards 1. Redesigned the switch Interface on the legacy cell controller to add a spatial multicast feature, implemented in a Xilinx 4013XL FPGA. 2. Developed behavior simulation models for all the active devices that connected to the switch fabric interface FPGA on the new, cost reduced cell controller card.