Phase 1:- Intro to Verilog- Difference between FPGA and ASIC- Combinational and sequential circuitsin Verilog- Synchronous and asynchronous reset- Blocking and Non-Blocking Statements- Finite State Machine (FSM)Phase 2:- Memory & Logic Arrays- Assembly Language- Intro about Microarchitecture- Single-Cycle & Multi-Cycle Processors- Pipelined Processor- Advanced Microarchitecture Phase 3:- Intro about verification andSystem Verilog- System Verilog Data types- Classes and OOP main concepts- Randomization & Constraints- Threads Inter-process- Functional Coverage- AssertionsPhase 4:- FPGA flow- ASIC flow- UVM

- VLSI, ASIC fundamental topics. [Full-custom VS semi-Custom, ASIC VS FPGA, ASIC Cost, Fabs VS Fabless companies]- CMOS basics review: CMOS characteristics (inverters), power consumption.- Introduction to PnR- Standard cell library/Macro views [.lef, .gds, .lib], .lib characterization.- Basics Microfabrication.- DFF architecture and requirements, metastability.- STA. [setup, hold, timing paths types] Constraints.- Timing paths reporting.- Logic synthesis. - DFT. - Low power techniques. [multi-voltage domains, clock gating, power gating, UPF map, multi-Vth]- Floor planning.- Power planning.- Placement.- CTS. [buffers, main concepts, NDR, constraints and goals, useful skew/CCD....] - Routing and chip finishing. - Power consumption and EMIR analysis.- Physical verification. [LVS, DRC, v2spi, DPT, SADP]

The content of my session:- Timing parameters - Setup & Hold time violations - Static Timing Analysis (STA)- Critical path and Slack representation - Clock parameters - Clock Domain Crossing (CDC)- Metastability solutions