Having graduated as a Telecommunication Engineer back in the day, I was always scared of working with FPGAs.The fear was always there but everything changed after I finished my PhD in 2019.I got my job as a Project Engineer on a very exciting project in the underwater acoustics industry.I worked with my team to design an underwater target detection system using digital hydrophone arrays.The associated digital signal processing for target detection was chosen to be implemented on FPGA/SoC and that is how my love for designing FPGAs started. Initially scared, I delved into the deep world of FPGAs and System on Chip (SoC) and started learning.I learnt about FPGA, VHDL and SoC from Muhammad Sadri, Russell Merrick and Jonas Julian Jensen. The toolchain of choice was Xilinx Vivado Design Suite for hardware design and Vitis for embedded design.I wrote custom IP in VHDL for part of my design as well as used existing IP in Vivado catalog for better design implementation. I partitioned the design with specific parts of design suited for FPGA implementation while the remaining parts implemented on ARM core using C/C++. I also learnt the ARM AMBA AXI protocol for designing custom modules with the right signalling knowledge for smooth data flow.I was able to use DMA for data transfer from DDR to FPGA.Following on, I have been continuing my passion for FPGA designing and currently working on High Speed Serial Links with AMD 7-series FPGA and Zynq Ultrascale/Ultrascale+ devices.I share my FPGA learning journey as well with my LinkedIn community from time to time and always looking for exciting challenges to implement algorithms on FPGA.
Listed skills include Telecommunications, Sdh, Fiber Optics, Iptv, and 26 others.