Anup J Deka Email and Phone Number

Responsible for end to end delivery of Integrated DC-DC Converters (FIVR), Bandgap Ref and Power Integrity Sensors IPs ensuring compliance to customers' requirements.

Design Manager of Digital Fully Integrated Voltage Regulator on latest Finfet process nodeDDR RX - Designed the receiver for next generation Memory IOs. Worked on a patented Decision Feedback Equalizer architecture and training algorithms.Clocking - Extensive experience in clocking circuits. Have worked on Self-biased & LC PLLs, DLLs, Phase Interpolators for 12 GTs SerDes and DDR, Duty Cycle Correction Circuits, Jitter Cancellation Circuits, High Speed SerDes Clock Distribution Led IP development of Buck Switching Regulator for next-generation Intel SoCs. Garnered experience of leading a team and designing an IP from scratch and this is complemented by strong Post-Si debug experience.PMIC/Haptics - Design fixes and Post-Si debug on DC-DC converters and Haptics.Voltage Regulators, Thermal Sensors - IP Lead for Thermal Sensors on Intel's next generation server products. Have worked on Voltage Regulators that support analog high performance or digital low power mode.Also have good knowledge of Static Timing Analysis, Reliability Analysis on FinFETs, Ageing, Noise Analysis. Have done extensive Post-Silicon work on PLLs and Thermal Sensors.

Executed a project “Design and Implementation of a low power Embedded System for monitoring Ion Beam Implantation Dose in a 1.7 MeV Tandetron Ion-beam Accelerator’’ under K.Suresh, Scientific Officer (E), Material Sciences Group, IGCAR