Eric P Email & Phone Number

United States

Austin, Tx, Us

Austin, Tx, Us

A research project was undertaken in collaboration between the University of Texas at Arlington (UTA) and the Interuniversity Microelectronics Center (IMEC). The research project, which concerns itself with the emerging interconnect exploration and technology/system co-design, employs a Linux operating system as the basis for its research and development platform. The research and development tool utilized is C++. The Cacti++ framework comprises Matlab and an executable file. As of the end of August 2024, eight papers have been published or accepted for publication on this subject, including those on TCAS-I, TED, TNANO, GLSVLSI, and ISQED.

Austin, Tx, Us

[1] Z. Pei, et al.,“Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus,”IEEE Transactions on Circuits and Systems I: Regular Papers,2024. DOI:10.1109/TCSI.2024.3438164[2] Z. Pei, et al.,“Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect,” in Proceedings of the Great Lakes Symposium on VLSI 2023,2023, pp. 159-162. DOI:10.1145/3583781.3590311[3] Z. Pei, et al.,“Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access,” in 2023 24th International Symposium on Quality Electronic Design(ISQED),2023,pp.1-1. DOI:10.1109/ISQED57927.2023.10129316[4] Z. Pei, M. Mayahinia, H.-H. Liu, M. Tahoori, F. Catthoor, Z. Tokei, and C. Pan,“Graphene-Based Interconnect Exploration for Large SRAM Caches for Ultrascaled Technology Nodes,”IEEE Transactions on Electron Devices, vol. 70, pp. 230-238,2022. DOI:10.1109/TED.2022.3225512[5] Z. Pei, F. Catthoor, Z. Tokei, and C. Pan,“Beyond-Cu Intermediate-Length Interconnect Exploration for SRAM Application,” IEEE Transactions on Nanotechnology,2022. DOI:10.1109/TNANO.2022.3157952[6] H.-H. Liu, C. Gilardi, S. M. Salahuddin, Z. Pei, P. Schuddinck, Y. Xiang, P. Weckx, G. Hellings, M. G. Bardon, and J. Ryckaert,“Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect,”IEEE Transactions on Circuits and Systems I: Regular Papers,2024.DOI:10.1109/TCSI.2024.3410518[7] H.-H. Liu, P. Schuddinck, Z. Pei, L. Verschueren, H. Mertens, S. M. Salahuddin, G. Hiblot, Y. Xiang, B. T. Chan, and S. Subramanian,“CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark,”IEEE Transactions on Electron Devices,2023.DOI:10.1109/TED.2023.3305322[8] M. Mayahinia, T. Marinelli, Z. Pei, H.-H. Liu, C. Pan, Z. Tokei, F. Catthoor, and M. B. Tahoori,"Dynamic Segmented Bus for Energy-Efficient Last-Level Cache in Advanced Interconnect-Dominant Nodes,"IEEE Embedded Systems Letters,vol.16,pp.321-324,2024.DOI:10.1109/LES.2024.3444711

Austin, Tx, Us

[11] S. Lu, Z. Pei, L. Shang, S. Jung, and C. Pan, “A Technology/Circuit Co-design Framework for Emerging Reconfigurable Devices,” in 2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS), 2023, pp. 1123-1127. DOI: 10.1109/MWSCAS57524.2023.10406005

Austin, Tx, Us

Electronics, Circuit Analysis, and Circuit Analysis with Lab.Beyond-CMOS Devices and Interconnect papers:[9] Z. Pei, A. Dutta, L. Shang, S. Jung, and C. Pan, “Interconnect Technology/System Co-Optimization for Low-Power VLSI Applications Using Ballistic Materials,” IEEE Transactions on Electron Devices, vol. 68, pp. 3513-3519, 2021. DOI: 10.1109/TED.2021.3077210[10] Z. Pei, L. Shang, S. Jung, and C. Pan, “Deep Pipeline Circuit for Low-Power Spintronic Devices,” IEEE Transactions on Electron Devices, vol. 68, pp. 1962-1968, 2021. DOI: 10.1109/TED.2021.3059601

Leuven, Be

A research project was undertaken in collaboration between the University of Texas at Arlington (UTA) and the Interuniversity Microelectronics Center (IMEC). The research project, which concerns itself with the emerging interconnect exploration and technology/system co-design, employs a Linux operating system as the basis for its research and development platform. The research and development tool utilized is C++. The Cacti++ framework comprises Matlab and an executable file. As of the end of August 2024, eight papers have been published or accepted for publication on this subject, including those on TCAS-I, TED, TNANO, GLSVLSI, and ISQED.

Orlando, Florida, Us

He has elected to transfer to the field of electrical engineering. His research interests include the theoretical aspects of reinforcement learning, control, and robotics.

Orlando, Florida, Us

His research interests include phase field modeling implemented in Matlab. Furthermore, he has received training in lithography and silicon wafer processing at semiconductor cleanrooms and labs.

Orlando, Florida, Us

He was awarded an ORC Doctoral Fellowship in the field of material science and engineering, which commenced in 2016. He subsequently completed the Qualifying Exams in the spring of 2017 and was subsequently appointed Graduate Teaching Assistant in the fall of the same year.[12] G. Jalilvand, O. Ahmed, K. Bosworth, C. Fitzgerald, Z. Pei, and T. Jaing, “Application of a metallic cap layer to control Cu TSV extrusion,” in 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 2017, pp. 61-66. DOI: 10.1109/ECTC.2017.290

San Jose, California, Us

SoC Realization Group (renamed as IP Group on Aug. 2013) R&DDesign DDR PHY IP for consumer electronics market. Debug relevant violations. Submit required files for fabrication/tapeout.Technology: TSMC 16FF, 28HPM, 28HPC, 28LP, SMIC 28HK.IP physical design for signoff & tapeout.Apply Cadence® EDA tools: Cadence® Innovus™ Implementation System, Encounter® Digital Implementation System (EDI), Encounter® Timing System (ETS), Tempus™, Physical Verification System (PVS), Encounter® Power System, Cadence® CMP Predictor, Cadence® Litho Physical Analyzer (LPA), Conformal® Logic Equivalence Check (LEC), Cadence® QuickView Signoff Data Analysis Environment, Cadence® Voltus™ IC Power Integrity Solution and etc.Understand Netlist, STA timing constraints, Opt Clock Tree Synthesis in CTS spec file based on design, clock tree structure, and timing, skew requirements.Familiar with the critical path and timing closure challenges in DDR PHY IP.Master physical design back-end flow, floorplan and place special instances on critical path manually based on design, STA timing and skew reports, CTS, routing, ECO, SDF ECO, assemble hierarchy (flatten partition).Debug violation on setup hold timing, skew, transition, duty, considering OCV derating, CPPR CRPR, SI, and etc. issue, congestion.Debug physical issue such as ANT, DRC, LVS, ERC; DFM/LPA CMP. Conformal. Power analysis. Submit clean GDS and relevant files for tapeout.Set MMMC corners and views based on release from foundries: TSMC, Globalfoundries, SMIC, such as RC extracting tech files etc.Teamwork with members. Collaborate with front-end engineers.• Developing and implementing timing ECOs including effect on congestion/routing/power.• Power-grid, clock tree, and low-power reduction implementation methods.• Signal integrity and timing closure issues.• Floorplanning, CTS, Placement, P&R.• Physical Verification, Conformal Low Power (CLP), IR drop analysis, Formal Verification.• Tcl, Perl.

Debug and test board level circuit of components in the device for the consumer market.Develop, debug, and test analog and digital circuits based on digital signal processing (DSP) and microcontrollers. The printed circuit board incorporates a DSP, power management circuitry, an analog-to-digital converter (AD), a preamplifier, and other circuit boards. Commercial products include the FlowQuest 600K, 1M, and 2M, as well as the FlowScout, which consists of a transceiver and a transponder.The circuits are designed to meet noise-tolerate requirement, and the boards are tested within the system. Additionally, the circuits are developed for use in medical imaging applications.Network Analyzer, Function Generator, Oscilloscope, etc.

Doctor Of Philosophy - Phd, Electrical Engineering

Doctor Of Philosophy - Phd Student, Transferred To The University Of Texas, Electrical Enginering

Doctor Of Philosophy - Phd Student, Passed The Doctoral Qualifying Exams, Material Science And Engineering

Master Of Science (M.S.)

Master Of Science (M.S.), Electrical Engineering