Working on AMD's ML Tools, Simulation, Debug and Profiling for AI Engine accelerator across Data Center, Client devices and Embedded systems.

Wide set of responsibilities :1. Vitis Emulation - Vitis is Xilinx's SW user focused IDE and tools set. My team is responsible for providing an emulator for the Xilinx DC and Edge platforms which enable a more SW like development flow for Xilinx users that provides quick compile and debug iteration, and can be executed without real hardware. My team developed from scratch infrastructure that enables hybrid simulation of components built using SystemC, RTL, Python, C/C++, and QEMU. The team provides an automated tool framework which is part of both Vivado and Vitis flows. The team also writes simulation models at required level of fidelity (Functional, Transaction Accurate, or Cycle Accurate). and in appropriate language and provides mechanism for other users to integrate their model into Xilinx tools.https://www.xilinx.com/products/design-tools/vitis.html 2. Vitis HLS Libraries - Focusing on data compression algorithms - GZip, LZ4 and implementing industry leading solutions optimized for FPGA based accelerator. - Provide easy to understand examples for SW users on github, tied with documentation. This is to enable Xilinx users the right programming patterns to get maximum performance out of Xilinx compilers and devices. This spans across examples for both data center and embedded focused devices.https://github.com/Xilinx/Vitis_Libraries3. Vitis Embedded Platforms- Lead team that builds Vitis Embedded Platforms. Enable key methodology shift by enabling HW, SW and Application parts to be developed independently. Provide pre-built platforms to enable early application and accelerator development. Prototype new architectures which can serve as reference for external customers.4. Xilinx Runtime (XRT)- XRT is Xilinx's unified runtime on both PCIe based DC and ARM based Edge platforms. My responsibility is to guide the team and coordinate with the San Jose based team.https://xilinx.github.io/XRT/master/html/index.html

1. Responsible for creation of custom Emulator for SW Developers working in Xilinx SDx Tools. This includes the SW and HW Emulator flows which rely on C and RTL Cosimulation, Qemu, XRT based interface with x86 application to provide a virtual platform for SW developer to run their application without requiring real hw board. This technology also drives System Level Simulation infrastructure and features for Vivado tools geared towards hardware users..2. Contribute towards compute acceleration over FPGA by prototyping K-means clustering algorithm in FPGA using OpenCL3. Responsible for EDA tool automation for complex Xilixn IPs like the DRAM Controller - MIG. This feature is used by almost all of Xilinx customers, requires interaction with all parts of the tool chain starting from front end GUIs to board design to back end place & route tools.

Engineering Manager and Architect for the Vivado IP Integrator tool. Hands-on leader guiding a team of experienced engineers in implementing this tool from ground up.Responsible for development cycle from start, leading through beta customer engagement, all the way through production. This tool has evolved into the mainstream design creation tool in Vivado and has extended well into Versal devices.

Hands on manager leading a team of 10 engineers working on the Xilinx Platform Studio (XPS). XPS represents an IDE and set of engine tools/flows enabling customers to assemble a SoC with processor and peripheral IP modules targeting Xilinx FPGAs.Responsibilities include working with the marketing team to determine and agree on new features for new releases of the products, do engineering resource planning and scheduling for implementation, quality and documentation. I am personally involved in details of feature planning. Sucessfully delivered 8 releases of the tool. This included significant updates to move from IBM's CoreConnect infrastructure to ARM's AXI, and migrating GUIs from Qt3 to Qt4, new OS Support, and several other significant features.Lead the work to model and integrate the ARM AXI based IPs into XPS including the ARM A9 processor. Other key projects included XPS GUI various Ease of Use Enhancements.Involved in engagement with customers to understand their issues and incorporate feedback for future releases. Involved in training of the FAEs (field) and providing inputs as needed.Link to product page: http://www.xilinx.com/products/design-tools/xps.html

SW Architect of the Xilinx Platform Studio (XPS) tools. This was the first System Level IP based SoC design tool at Xilinx encompassing both HW and SW aspects. I was the software architect who organized the code into various modules and established key coding methodology used by other developers. I wrote the very first line of the datamodel on which the whole code-base operates. The code written remains foundation of the entire software product its entire life of 10+ yrs. The code has stood the test of time and has been able to successfully handle several new requirements over a period of several years.Developed new key concepts in terms of hardware modeling (IPs, Boards) and tool meta-data to capture necessary information. The IP modeling concepts were so cleanly developed that most of them map directly onto the XML based industry standard IP-XACT (IEEE 1675), which was developed much later.Worked on flow integration with other Xilinx design/debug tools like Project Navigator, SysGen DSP, Chipscope, MIG (Memory Interface Generator). Was the key person involved in discussion of flow integration with other third party tools like Synopsys Synplify, National Instrument's LabView, and Mentor's HDL Designer.Worked on Xilinx Virtual Platform Generation frame-work to simulate a processor based system using cycle accurate C-model. The tool assembled either C-models for various IPs into a system as designed by the user, and integrated into a clock based simulation engine. The C-models were either hand-written or generated dynamically based on synthesizable HDL.Worked with other team members on software flows including driver compilation, BSP generation.Projects were implemented in C++ with extension points for TclPatents:1. Method and apparatus for providing self-implementing hardware-software libraries2. Framework for cycle accurate simulation

Senior Software Engineer part of the Emerging Technologies Group. Key projects include FPGA Architecture Evaluation, Improving timing estimation for synthesis, developing concept of the Anyware tool to enable switching between hardware and software implementation based on a library of modules.Patents:1. PLD configurable logic block enabling the rapid calculation of sum-of-products

Worked on the timing simulation for DRAM memory chip