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Technology Leader with 13 years of Semiconductor Industry experience. Worked on Product definitions and architecture performance evaluation. Executed projects from bare-bones in System Solution Development (HW/SW/Algorithm/Host SW), Silicon Bring-up, Digital & Mixed Signal IC Bring-up, DSP Application Development, Boot ROM Development, and Firmware Driver. Worked with Customers across the globe and supported them in their solution development with CPU, DSP, and Digital and Mixed Signal IC. Well-versed with silicon-to-system developmental challenges and Function Safety methodologies. Worked across multiple product lines from CPU, DSP, Audio, Automotive, Electric Vehicles, and Radar. Experience with team building and managing high-performing teams performing multiple post-silicon functions, prototyping, and system solution development. Worked in and with teams across multiple regions of the globe. A quick learner with a problem-solving mindset and always looking to learn and improve technical and management skills. I hold an M.S. (Master of Science) in Computer Engineering from Northeastern University, Boston & a Diploma in Embedded System Design from CDAC-Hyderabad, and a B.E (Bachelor of Engineering) in Electronics from Nagpur University, India. I completed the Executive General Management program from IIM-Bangalore to enhance my Business, Product, and Team development acumen.
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Principal EngineerMips Dec 2022 - Jul 2024Bengaluru, Karnataka, IndiaP8700 is an out-of-order, Multi-Cluster, Multi-Core, and Multi-Hart, Out-of-order CPU based on the RISC-V architecture. Responsible for the FPGA-based evaluation platform, software development, Performance evaluation, and customer support for the same. Designed and defined FPGA-based SOC with the CPU, ported bootloader, and Linux for the FPGA-SOC. Ported, and created a framework for benchmarking CPU for both Bare Metal and Linux environments. Designed and developed a complete automated functional and performance regression environment to help in tracking functional and performance evaluation file RTL bugs from FPGA and help in RTL bug prioritization and resolution -
Senior Application And Marketing ManagerAnalog Devices Jan 2018 - Dec 2022Bengaluru, Karnataka, IndiaBattery monitoring is a critical function of an Electric Vehicle In this role started with understanding the EV system, Battery monitoring, and the associated IC’s functionality. Worked in the development of ISO26262 Compliant Validation Firmware and Framework for the complete product family. Supported customer's queries on the product line, and enhanced customer release firmware to meet their customer test/integration requirements. During customer support for 4-WH, a gap in the product portfolio for 2-WH was identified. Worked on the product (ADBMS6948) definition, product development, product validation& characterization for the newly defined product. Develop a complete reference solution including the Reference Hardware, Middleware, Firmware, and Host SW which showcased the completed feature set of the product along with the key battery algorithms like State of Charge and Health with data collected in real-time. Built a 15-member strong and high-performing team comprising both Senior and New College Graduates. Mentored and guided them to perform activities across HW Board design, ISO26262 Compliant Validation, Bench Test Setup, and Software Development, Board Design and supported customer queries related to all ADBMS products at Analog devices -
Lead Product Applications EngineerAnalog Devices Jul 2016 - Apr 2018Bengaluru, Karnataka, IndiaWorked as Individual and Lead for Multiple products, 1st project was Magnetic Sensor Evaluation and Characterization the project involved an analog front end and digital back end. This was the 1st Mixed Signal IC Characterization activity, ramped up on Analog Characterization, and developed a completed LabVIEW framework for the Validation and Characterization of the IC. Developed Test plans, and test cases to comply with ISO26262 standards. The IC had an analog front end which gets the input from the AMR sensor which detects change in magnetic field direction, the digital data is then given to a CORDIC block which then calculates the angles, and the angle is transmitted over the SPI interface. The IC was ASIL-D Fail operational design so there were multiple redundancies and significant digital software required for configuration. Developed a reference system solution for the customer for the same IC. The 2nd project was a DSP Test Chip based out of Ten silica Core IP, I was responsible for both Performance and Functional evaluation, worked on the firmware development for the DSP Test Chip, and ported system-level application software use cases -
Product Application EngineerAnalog Devices Apr 2013 - Jun 2016Norwood MaWorked on various projects across the DSP SOC domain. Started with understanding and brought up a new DSP- BF70x, especially around the power mode transition, and then moved on to work on bring-up and firmware development for the new peripherals like Trigger Routing unit, Core Sight debug, and Trace. Developed a ground-up understanding of the blocks and authored app-note and training material for these and other blocks for the DSP. Supported customers for queries and solution development with the DSP. Worked with the design team for various test firmware and solution development across different areas of the DSP, like cache performance analysis, Automation of ATE test code on the Hardware, and script development for datasheet and product reference manual. During the same phase worked on the Bring-up firmware of the Cortex-M4 product for the core, CORDIC, and Math accelerator blocks.Developed a complete reference solution for 24GHz Radar solution development with BF70x, ramped up on the radar system and algorithms. Developed the complete reference firmware & middleware and application Software for DSP which was the only control in the solution. The firmware involved configuring the Radar Chipset (ADF5901, ADF5904, AF4159) and Multi-Channel ADC(ADAR7251) collecting data on the DSP on the Parallel port interface, and then doing parallel FFTs on the data and then transferring the Range, Velocity and Ange of the target on a host SW for visualization. The system solution was fully developed from scratch, tested, and now is available as a reference 24Ghz Development kit -Eval-DEMORAD from ADI -
Co-Op Dsp Application GroupAnalog Devices Jul 2012 - Nov 2012Norwood MaDeveloped DSP test application on power mode transitions and estimation. Replicated & Debugged issues related hardware and software on dual core DSP (BF-609) also developed power mode estimation spread sheet which estimates power consumtpion under different load profiles. The work involves using assembly and Embedded C programming.Developed a methodology to determine cache size using cache simulator .Project involves developing a tool which simulates different cache configuration. The access patterns are captured using a cycle accurate simulator and then modified and feed to a cache simulator which provides statistics for different cache configuration. The tool will help to determine the optimal cache configuration of a SoC. The work involves using the Synopsys Virtual Platform analyzer, Dinero tools and Python, and TCL -
Graduate Research AssistantNortheastern University Sep 2010 - Apr 2012Greater Boston AreaWorked as Research Assistant for a Versatile Onboard Traffic Embedded Roaming Sensors (VOTERS) project which aims to shift from periodical localized inspection of roads and bridge decks to using commercial fleet vehicles for the data collection and then backend system to analyze and create work orders for road repair and maintenance departments. Architected and developed the firmware for the Single board Controller on the unit, which was responsible for interfacing, and configuration from all 6-analog Sensor, doing 1st level of data fusion and processing, and then transferring the data back to the host system for critical data in real-time and complete transfer when the vehicle comes to complete halt. The complete firmware was developed on C++ and QNX systems -
Software EngineerMahindra Satyam Apr 2008 - Jul 2010Bangalore ,Karnataka, IndiaJoined as a software engineer and worked on various embedded firmware and software projects across the Automotive and Consumer domains. Worked on the complete revamp of the boot loader and firmware for ECUs for Heavy Automotive Vehicles to support secure and wireless boot systems. Worked on the test and bring-up of ECU. Worked on firmware development of the memory management system, device drives, and wireless modules for printers.
Akash Agarwal Skills
Akash Agarwal Education Details
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Completed -
Cdac-HydA -
First Division
Frequently Asked Questions about Akash Agarwal
What is Akash Agarwal's role at the current company?
Akash Agarwal's current role is Principal Engineer at MIPS, Ex ADI, IIMB -Alumnus, NEU-Alumnus, CDAC-HYD.
What is Akash Agarwal's email address?
Akash Agarwal's email address is ak****@****log.com
What schools did Akash Agarwal attend?
Akash Agarwal attended Northeastern University, Indian Institute Of Management Bangalore, Cdac-Hyd, Nagpur University.
What are some of Akash Agarwal's interests?
Akash Agarwal has interest in Exploring Places And People.
What skills is Akash Agarwal known for?
Akash Agarwal has skills like Embedded Systems, C++, C, Assembly, Python, Tcl, Perl, Arm, Soc, Computer Architecture, Open Source, Linux.
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