Akash Reddy Ravula Email & Phone Number

I possess a Master's degree in Electrical Engineering, specializing in Electronics and Mixed Signal Circuit Design from Arizona State University (ASU). Currently, I am employed at Broadcom as an IC Design Engineer, contributing to the ASIC Products Division (APD). Previously, I worked at Seagate Technology as a System-on-Chip (SoC) Engineer, where I focused on synthesis, formal verification, and static timing analysis within the VLSI SoC development organization.My academic journey has honed my expertise in digital IC design, Verilog, Static Timing Analysis, logic design, and design automation tools. I am proficient in using Synopsys Design Compiler, PrimeTime, Formality, VC SpyGlass, Cadence Innovus, Virtuoso, Modelsim and HSPICE. Additionally, I earned certifications from Cadence Design Systems in basic static timing analysis and RTL-to-GDSII flow. My experience as a Teaching Assistant for Circuits-I at ASU allowed me to provide valuable guidance and feedback to students, fostering their understanding of circuit analysis and design principles. As a Research Intern at Research Centre Imarat (RCI), I designed and verified low-power digital circuits for radar systems, gaining hands-on experience. I am always eager to connect with industry professionals and explore opportunities for collaboration and growth. Feel free to reach out if you would like to connect or discuss potential opportunities.