Corporate Vice President
CurrentCVP IO Architecture , Responsible for I/O and Interface IP Architecture
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@amd.com
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Anwar Kashem is listed as CVP IO Architecture @ AMD at AMD, a with 16705 employees, based in Sudbury, Massachusetts, United States. AeroLeads shows a work email signal at amd.com and a matched LinkedIn profile for Anwar Kashem.
Anwar Kashem previously worked as Corporate Vice President at Amd and Senior Fellow at Amd. Anwar Kashem holds Ms from Cornell University.
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I am an experienced Architect with a demonstrated history of delivering innovative solutions in the semiconductor industry. My most recent roles include Architectural Definition for internally developed SoC/ASSP/CSSP products, and also for customized silicon solutions for partners and end-customers.I have led global engineering teams and worked as a strong individual contributor across all levels of design abstraction {Architecture, Software, Firmware, Customer Enablement, Platform design, RTL Design, Physical Design, and Custom Circuit Design}.
Listed skills include Phy Architecture, Clock Generation And Distribution, Fpga Fabric Design, Dram Interface Design, and 26 others.
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Boxborough, Massachusetts, United States
CVP IO Architecture , Responsible for I/O and Interface IP Architecture
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Anwar Kashem works for AMD.
Anwar Kashem is listed as CVP IO Architecture @ AMD at AMD.
AeroLeads has found 1 work email signal at @amd.com for Anwar Kashem at AMD.
Anwar Kashem is based in Sudbury, Massachusetts, United States while working with AMD.
Anwar Kashem has worked for Amd, Marvell Semiconductor, Synopsys, Achronix Semiconductor, and Advanced Micro Devices.
Anwar Kashem's colleagues at AMD include Sesi Jeanett Tsotetsi, Swati Kriplani, Israel Asfaw, Kris Socha, and Biju Odayammatath.
You can use AeroLeads to view verified contact signals for Anwar Kashem at AMD, including work email, phone, and LinkedIn data when available.
Anwar Kashem holds Ms from Cornell University.
Anwar Kashem is listed with skills including Phy Architecture, Clock Generation And Distribution, Fpga Fabric Design, Dram Interface Design, Silicon Debug, Multi Clock Timing Analysis, Power Management, and Rtl Design.
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