Akhil Jain Email & Phone Number

Santa Clara, Ca, Us

Santa Clara, California, United States

Santa Clara, Ca

• Part of Hardware operation group leading multiple high-speed interconnect products. • Collaborate with design, test, foundry, supply chain and reliability engineering to drive NPI DFM and meet NPI deliverables and milestones. • Characterize NPI product performances and yield including bench correlation to meet product cost targets.• Provide regular NPI Ops status update to cross-functional team.• Define process corners and product process targeting from characterization… Show more • Part of Hardware operation group leading multiple high-speed interconnect products. • Collaborate with design, test, foundry, supply chain and reliability engineering to drive NPI DFM and meet NPI deliverables and milestones. • Characterize NPI product performances and yield including bench correlation to meet product cost targets.• Provide regular NPI Ops status update to cross-functional team.• Define process corners and product process targeting from characterization results.• Work with test engineering to ensure NPI meets production release requirements and successful bring up at OSAT.• Identify and drive production capacity improvement needs via yield improvement, test time reduction, first pass retest rate reduction and qualifying alternate sources.• Provide product engineering support to customer returns working laterally with Quality, Design and Test engineering in a timely manner. Show less

Santa Clara, Ca

• Leading a team of engineers in qualifying various server products for complete design validation including pre-silicon testing, electrical validation, and high volume manufacturing. • Layout execution strategy, highlight any risks and make sure overall product quality and product availability meet all requirements.• Identify gaps and deficiencies in existing test plans, scripts, and cases, and effectively extend test plans where necessary. Work with design to help troubleshoot… Show more • Leading a team of engineers in qualifying various server products for complete design validation including pre-silicon testing, electrical validation, and high volume manufacturing. • Layout execution strategy, highlight any risks and make sure overall product quality and product availability meet all requirements.• Identify gaps and deficiencies in existing test plans, scripts, and cases, and effectively extend test plans where necessary. Work with design to help troubleshoot defects.• Leading effort to optimize test flows for efficiency, improve test time and coverage.• Drive weekly forums with stakeholders to brainstorm and prioritize various issues at hand.• Write documentation on various standardization efforts so that other teams can utilize various templates with a minimal pass down. • Expertise in failure analysis, test content development, bench debug, tester debug, characterization, yield analysis, yield improvement and test time reduction for NPI as well as sustaining products. • Mentor team members and encourage others to meet the established objectives.Recognitions• Recognized with BU level award for coming up with the lowest cost and lowest maintenance solution for per pin leakage test across product lines saving Intel more than $10 million. • Exploration complete award for substantially reducing I/O test time to achieve a 50% reduction in test time. • Server development and Manufacturing award for dedication and teamwork that lead to root causing multiple IO design bugs which lead to yield improvement of 3%-5%. Show less

Irvine, Ca

• Interacting with various internal business units for qualifying OTP and troubleshooting related issues on various products for 65nm technology by working with their Design, Product and Test engineers.• Responsible for debugging ATE and bench related issues during qualification of OTP and RF/FSRF test chips. • Responsible for qualifying 40nm test chip with memory instances like RF/FSRF/ROM for various design parameters like screening, functional test, VCCMIN test, Access time… Show more • Interacting with various internal business units for qualifying OTP and troubleshooting related issues on various products for 65nm technology by working with their Design, Product and Test engineers.• Responsible for debugging ATE and bench related issues during qualification of OTP and RF/FSRF test chips. • Responsible for qualifying 40nm test chip with memory instances like RF/FSRF/ROM for various design parameters like screening, functional test, VCCMIN test, Access time test.• Responsible for test chip qualification for 180nm, 65nm, and 40nm one time programmable (OTP) ROM.• Responsible for tracking 65nm and 40nm test chips from its tape out to final product and make sure respective design and product engineers are aware of various details like splits, quantity, foundry.• Helped in debugging issues related to un-intentional programming and skipped bits while qualifying various products with OTP• Investigated functionality issue on RF memory because of weak core PMOS device resulting in the foundry (TSMC) improving their process. Show less

Boise, Idaho Area

• Responsible for simulation and coordinating with the designers on various issues related to first silicon for DDR3, LPDRAM.• Responsible for regularly analyzing Backend and Probe data to check for any sudden fallout in the manufacturing facility in turn enhancing functionality and improve overall yield of memory products.• Responsible for conducting Product Update meetings with our overseas counterpart. • Bench debug and characterization of memory devices to investigate design… Show more • Responsible for simulation and coordinating with the designers on various issues related to first silicon for DDR3, LPDRAM.• Responsible for regularly analyzing Backend and Probe data to check for any sudden fallout in the manufacturing facility in turn enhancing functionality and improve overall yield of memory products.• Responsible for conducting Product Update meetings with our overseas counterpart. • Bench debug and characterization of memory devices to investigate design, process and test related fails.• Investigated a refresh related fail using simulation and bench testing. Determined and verified the fix on device and proposed reticle edit. Significant yield loss was avoided as a result. • Formulated fixes for various device functionality, speed and testability issues using software tools, circuit analysis and data mining. Show less

Roseville, Ca

• Worked on Annealing tools like Heatpulse and Centura for Thin Films.• Familiarization with the IC manufacturing flow and various post silicon processing tools which involves working inside the fabrication facility.

Ms, Electrical Engineering

Be, Electronics Engineering