Akhil Jain Email & Phone Number

Santa Clara, CA, US

Santa Clara, California, United States

Santa Clara, CA

• Part of Hardware operation group leading multiple high-speed interconnect products.
• Collaborate with design, test, foundry, supply chain and reliability engineering to drive NPI DFM and meet NPI deliverables and milestones.
• Characterize NPI product performances and yield including bench correlation to meet product cost targets.
• Provide regular NPI Ops status update to cross-functional team.
• Define process corners and product process targeting from characterization… Show more
• Define process corners and product process targeting from characterization results.

Santa Clara, CA

• Leading a team of engineers in qualifying various server products for complete design validation including pre-silicon testing, electrical validation, and high volume manufacturing.
• Layout execution strategy, highlight any risks and make sure overall product quality and product availability meet all requirements.
• Identify gaps and deficiencies in existing test plans, scripts, and cases, and effectively extend test plans where necessary. Work with design to help troubleshoot… Show more
• Identify gaps and deficiencies in existing test plans, scripts, and cases, and effectively extend test plans where necessary. Work with design to help troubleshoot defects.
• Leading effort to optimize test flows for efficiency, improve test time and coverage.
• Drive weekly forums with stakeholders to brainstorm and prioritize various issues at hand.

Irvine, CA

• Interacting with various internal business units for qualifying OTP and troubleshooting related issues on various products for 65nm technology by working with their Design, Product and Test engineers.
• Responsible for debugging ATE and bench related issues during qualification of OTP and RF/FSRF test chips.
• Responsible for qualifying 40nm test chip with memory instances like RF/FSRF/ROM for various design parameters like screening, functional test, VCCMIN test, Access time… Show more
• Responsible for qualifying 40nm test chip with memory instances like RF/FSRF/ROM for various design parameters like screening, functional test, VCCMIN test, Access time test.
• Responsible for test chip qualification for 180nm, 65nm, and 40nm one time programmable (OTP) ROM.
• Responsible for tracking 65nm and 40nm test chips from its tape out to final product and make sure respective design and product engineers are aware of various details like splits, quantity, foundry.

Boise, Idaho Area

• Responsible for simulation and coordinating with the designers on various issues related to first silicon for DDR3, LPDRAM.
• Responsible for regularly analyzing Backend and Probe data to check for any sudden fallout in the manufacturing facility in turn enhancing functionality and improve overall yield of memory products.
• Responsible for conducting Product Update meetings with our overseas counterpart.
• Bench debug and characterization of memory devices to investigate design… Show more
• Bench debug and characterization of memory devices to investigate design, process and test related fails.
• Investigated a refresh related fail using simulation and bench testing. Determined and verified the fix on device and proposed reticle edit. Significant yield loss was avoided as a result.

Roseville, CA

• Worked on Annealing tools like Heatpulse and Centura for Thin Films.
• Familiarization with the IC manufacturing flow and various post silicon processing tools which involves working inside the fabrication facility.

Ms, Electrical Engineering

Be, Electronics Engineering