Akram Issa Email & Phone Number

Greater Toronto Area, Canada

Responsible for planning, directing daily activities, and providing direction to Logic design team with meeting schedule and quality.● Plans, provides resources for, and directs activities to IP logic design team from concept feasibility stage to product enablement with meeting schedule and quality.● Define and develop logic design features working with system group and array group.● Guidance of Complex RTL logic design and Firmware to meet performance and area.● Staffs, defines roles & responsibilities, and provides guidance on employee development, performance, and productivity issues.● Cross functional work and strong team player for the success of SoC IP products

United States

● Working across multiple teams of SoC server CPU structural logic design teams to provide IP solutions including Scalable Coherent Fabrics, Power Management Solutions, Debug Solutions and System Management Utilities.● Creating Micro-architecture for various blocks, and RTL development using SystemVerilog.● Write technical product documents to assist our customers with the use of our IP TRM (Technical Reference Manual). ● Estimate power for blocks using EDA tools and create power models.● Streamline the production, delivery/release and consumption of our IP using Python scripting

United States

● Working on multiple IP design that includes:● Micro-architecture design and implementation for SERDES ADPLL in 10nm intel process.● Micro-architecture design and implementation for MIPI I2C/I3C V1.1 Host controller IP in 22 nm TSMC process.● HDMI 2.1 transceiver design prototype. 10nm Chip, and Google Pixels TPU 5nm product, ● RTL development for various blocks using System Verilog.● Worked with architects/logic designers/DV to define, implement the power system requirements UPF using VCLP and sign-off using generated test vectors in PTPX tool.● Analyzed power data and worked closely with PD and design team to optimize for low power and improve overall PPA.● Work in cross function team to deliver FPGA prototyping using Xilinx Vivado, and High-level synthesis tools.

San Diego County, California, United States

- Participated in the design of multiple SoC design, that included ● Digital SoC micro-architecture design and implementation of next generation 2x2 MIMO 802.11ax Wi-Fi6 devices. ● Completed Micro-architecture and RTL design for Frequency Encoder/Decoder 2x2 PHY design. ● Participated in the design of multiple SoC Network-On-Chip (NoC) architecture to meet the PPA performance. ● Supported Source Synchronous clock implementation, low power design and area management.● Explored architecture trade-offs in system performance, area, latency, and throughput. ● Developed a complete high performance 1GHz AXI/AMBA Traffic Generators in SystemVerilog RTL environment.● Worked closely with the ASIC architecture, and PD team to resolve any issues related to ECO, FV, ● Developed scripts required to use the synthesis tools and the analysis of the results. ● Developed timing constraints, Clock-Tree constraints, and analyzed timing results from layout.

Wilmington, Massachusetts, United States

● Worked as a principal ASIC designer / team lead for mixed signal wireless transceiver products. ● Cartesian RFIC Baseband chip, and high speed 4GSPS ADC/DAC products.● Successfully completed RTL development and implementation of Digital Signal Processing (DSP) algorithms (CORDIC, NCOs, multi-rate filter FIR/IIR, and Direct Digital Synthesizer DDS) into 2GHz SoC. ● Technical lead for 3+ engineers on digital blocks to be designed, using ASIC tools. ● Developed scripts required to use the synthesis tools and the analysis of the results. ● Developed timing constraints, Clock-Tree constraints, and analyzed timing results from layout. ● Oversaw design and development of SoC systems from specification through to production ready phases. ● Interacted with counterparts on Software, System, verification, and Back-End engineering teams to ensure project scope met specifications. Led/Attended and participated in detailed design reviews. ● Planned, aligned and directed efforts of electrical engineering team, creating culture of teamwork to realize goals and objectives.

Cambridge, Ontario, Canada

● Developed several low power/high speed Broadband Satellite Base-band products. ● This included, a single carrier QPSK modem, a GPRS 2.5G Handheld device, OFDM Power line AV Modem, and Digital Pre-distortion DPD for high performance Power Amplifier. ● Completed OFDM Baseband RTL modem design working on Mapper/De-Mapper for 1024 QAM modulator.● Implemented full DSP functions which included 384/3072-point FFT/IFFT ● Completed efficient DSP RTL algorithm development for CCD imaging technique, and modeling using MATLAB, and C language. ● Written Micro-architecture specifications for various blocks to be developed. ● Designed the blocks by utilizing Verilog-HDL. ● Performed and completed functional simulations. ● Synthesized the design and performed/completed STA. ● Prepared for technical reviews and completed product documentation. ● Mentored the junior engineers throughout the development cycle.

Ottawa, Ontario, Canada

● Working as a member of IC Switching design engineering team to develop 2/8 Gbit Ethernet Switch. ● Working on the Engress engine to develop the TCAM (Ternary Content Addressable Memory) controller. ● Participating in the design reviews and the Marketing Requirement Design (MRD) document.● Conducting a feasibility study on the size of the module to be designed as well as the best-optimized way to reduce cost and power consumption.● Writing the technical specification for the ASIC module to be designed● Implementing the design according to the technical specification using Verilog.

Ottawa, Ontario, Canada

● Working as a member of IC design team for the Digital Message Switch (DMS) PowerPC604-to-PCI bridge controller.● The design of a Line Card controller (ATM/ADSL Multiplexing), using Altera MAX7000 series ● The design of a VIM Interface Card design for a Wireless application, using Xilinx Virtex-II ● The design of a PCI-to-SDRAM Controller, using Xilinx Virtex-I ● Working on ATM UTOPIA level1/2 for OC-12/192 optical transceiver design.● Implementing the design according to the technical specification using VHDL. ● Conducting a feasibility study on the size of the module to be designed as well as the best-optimized way to reduce cost and power consumption

Master Of Science - Ms, Electrical And Electronics Engineering

Activities and Societies: Master of Science in Digital IC design on Speech processing

Bachelor Of Applied Science - Basc, Electrical, Electronics And Communications Engineering