Architect Intern
SoC Performance ModelingContributed to SoC Full Chip Modeling team by integrating an ARM Coherent Mesh Network (Cyprus) FastModel into the existing C Model, designing mesh configurations for various core numbers and memory region requirements.Developed firmware using C++, SystemC, TLM 2.0, and AMBA PV extensions to program CMN configuration registers, ensuring timely booting and accurate routing of memory transactions to ensure coherency.Validated the changes with ~500 tests, including coherency tests and a kernel boot.