Alan Langdon Email & Phone Number

Wayne, Pa, Us

Blue Bell, Pennsylvania, Us

PRINCIPAL ENGINEER, MCP Processor Emulation Delivered and maintained 10 generations of software-based (C++) central processing modules (CPM) within ClearPath Forward Libra and ClearPath MCP Software systems.Processor architecture and design expert: Performed all aspects of processor definition, development, implementation, optimization, evaluation, verification, and support.● Defined and integrated architectural changes, expanding capacity limits and enabling performance improvements (E-mode level Eta).● Restructured and ported legacy hardware, operator-level verification suite from assembly code to high-level language (NEWP) suitable for software-based designs, extending coverage for architectural evolution and expanded operator set.● Achieved 20% performance increase by conceiving and implementing speculative data type-based execution.● Uncovered numerous design vulnerabilities and integrity issues through inspection, verification, and support activities, ensuring all were driven to root cause, understanding, and resolution.● Advanced technical understanding, mentoring junior engineers and contributing to knowledge management repository.System-level expert: Consulted and interfaced between processor, operating system, compiler, performance, and architecture teams.● Analyzed and drove resolution of complex cross-functional issues, addressing vulnerabilities, integrity failures, and performance irregularities.● Guided performance benchmarking, performance metering, and consumption reporting methodologies, delivering consistent and innovative market-driven pricing to clients.

Blue Bell, Pennsylvania, Us

PRINCIPAL ENGINEER, MCP Accelerator Fpga (Mach1) Redesigned and ported existing Central Processor and Node Controller ASIC designs (130/90 nm) into FPGA / structured ASIC-based solution using Altera's 40 nm HardCopy technology.● System-level architect: Collaborated from project conception on architecture definition, performance evaluation, maintenance design, console interface, and vendor and technology selection. ● Instruction Processor co-architect: Influenced all aspects of development, including feature set, initialization, testability, diagnostic collection, fault reporting and isolation, features for contingency operation, SER analysis, and time-of-day operation.● Sole developer for IP Execution Unit: Defined, implemented, and verified RTL (VHDL) pipeline restructuring, algorithm adaptations, timing, and iterative physical design optimization, meeting performance and stretch frequency goals ahead of schedule.

Blue Bell, Pennsylvania, Us

PRINCIPAL ENGINEER, MCP Processor ASIC DevelopmentRedesigned existing Central Processor into 130 nm ASIC technology, introducing dual-core architecture, 100% single-thread performance increase, and integration into common server platform (licensed Intel front-side bus protocol).Processor architect and designer:● Represented processor team, interfacing with Operating Systems, Systems Management, Maintenance, Firmware Development, Performance, and Capacity-on-demand / Metering groups.● Increased clock-for-clock performance 33% by collaborating on architectural improvements.● Innovated new test methods, enhancing expectations of program success.o Conceived and designed automated method for dynamic variation of static stress switches, ultimately leading to discovery of 4 critical ASIC logic design bugs prior to pass-2 release.o Directed staged single unit / hierarchical unit test methodology, allowing quick and efficient hardware test progress.● Drove cross-functional triage analysis and problem resolution, exceeding product release and customer satisfaction commitments.● Provided complete response to excessive soft error incidence at customer sites. Performed root-cause analysis, released mitigating design changes, and developed lab tests to demonstrate out-of-spec behavior, leading to confirmation of supplier's use of incorrect solder paste.Unit-level lead:● Defined and delivered technology and evolutionary updates to Central Processor Execution Unit, driving all aspects of functional changes, RTL implementation, timing, floorplanning, microcoding, simulation, verification, integration, debug, and qualification.● Directed junior engineers with unit-level assignments, building effective team and encouraging individual growth.

Blue Bell, Pennsylvania, Us

PRIOR ENGINEERING ROLES, MCP Processor ASIC Development pre - 2003Developed and maintained 5 generations of proprietary ASIC / PCB-based central processing modules (CPM) through their full engineering lifecycle, delivering world-class, mission-critical solutions within Unisys MCP mainframe systems.

Bachelor Of Science - Bs, Electrical Engineering

Bachelor Of Science - Bs, Electrical Engineering