Alan Ellis Email and Phone Number

Responsibilities include the design & evaluation of RF integrated circuits which support the company's Wireless Infrastructure product portfolio.Ongoing projects include:• Designing a GaN Power FET Controller which is targeted to be used with Qorvo’s suite of GaN Power Amplifier portfolio. This controller solution includes 30V+ drain current sensing, a negative voltage charge pump, ADC, temperature sensor, and waveform shaping to maximize power efficiency. • Designed a Temperature-to-Digital Sense circuit for a Dual LNA + DSA (Digital Step Attenuator) Module Controller in 0.18um bulk CMOS. Temp range is -60C to +140C converted into an 8 bit word. • Designed a set of Power Log Detectors in CMOS to be used in PA modules with power control feedback loops. • Designed a high-linearity stacked-FET configurable programmable linear-in-dB coefficient VCA (Voltage Controlled Attenuator) and programmable linear-in-dB coefficient TCA (Temperature Controlled Attenuator) in IBM’s CSOI7RF 0.18um CMOS Silicon-on-Insulator process. US Patent granted. • Modified a high-frequency high-linearity VCA in CSOI7RF. Stacked-FETs are used to enable operation at input power levels up to 30dBm across a wide signal bandwidth (50MHz – 20GHz). The large signal settling time for a 20dB step in input power is less than 2us.

Responsibilities include developing proprietary system control circuits for a chip design which will increase the battery life of 2G, 2.5G, 3G, & 4G mobile handsets.Completed project items include:• Developed a high efficiency control system for a Buck converter which included a glitch-free automatic switchover between the PWM (Pulse Width Modulation) mode when the converter was operating in the Continuous Current Mode (under high current loads) to a Hysteretic mode or to a PFM (Pulse Frequency Modulation) mode when the converter was operating in the Discontinuous Current Mode (under low current loads). The control system also included an OCP (Over Current Protection) detection circuit. Circuit hooks were included to support a future feature to maintain a constant small signal modulation bandwidth when the converter crosses between the CCM & DCM regimes (for Envelope Tracking schemes).

Responsibilities included being the Project Lead for the development of a proprietary method of Small Signal Open Loop Polar GMS/EDGE transmission. Emphasis was placed on an architecture which may have been suitable for future 3G polar transmitter development.Completed projects included:• Designed the system & specifications for a proprietary 2.5G GSM/EDGE Small-Signal Polar Transmitter, which included calibration schemes for the Magnitude Path Timing Skew, the Magnitude Path Filter BW, the Phase Path Timing Skew, and the Frac-N PLL Modulation BW. - Modeled the entire system in Mathwork’s SimuLink including the CORDIC (COoRdinate DIgital Converter), Phase Path Pre-Distortion, Frac-N PLL (Phase Locked Loop), ΣΔ DAC (Digital to Analog Converter), Filters, VGA (Variable Gain Amplifier), & RF Driver blocks. - Collaborated in modeling the entire system in Mathwork’s MatLab. - Designed/Modified the High Band & Low Band RF Driver blocks.• Modified an existing RX path ΣΔ ADC to include a new Zero-IF mode (as well as keeping the existing Low-IF mode) of operation.• Assisted in the system design of a TD-SCDMA transceiver design.

Responsibilities included the design and evaluation of circuits which contain the analog and mixed-signal cells necessary to implement a proprietary method of IR (Image Reject) calibration for a transceiver RX path, a low phase noise GMSK capable LC Tank VCO for LO (Local Oscillator) generation, and the control/protection circuitry for a proprietary, CMOS PA (Power Amplifier) design.Completed projects included:• Designed a 2GHz upconversion active mixer & supporting circuitry to realize a new proprietary method of single LO IR calibration for the RX path in 0.13um CMOS.• Designed an 8GHz LC Tank VCO for GMSK TX LO generation in 0.13um CMOS, where the area is 0.376mm2.• Designed/modified various analog control & protection circuitry for a proprietary CMOS PA amplifier.

Responsibilities included the design and evaluation of circuits which contain the analog and mixed-signal cells necessary to support a OC-192 Optical Transceiver design in 0.13um CMOS (Agere’s FLEXPHY[tm] chip). Completed projects included:Agere Systems - San Jose, CADMTS Analog Design Engineer – Ethernet Division• Participated in a pilot project to implement 802.11af Power-Over-Ethernet capability via an electrically isolated transformer configured as a flyback DC-DC converter. Patent Pending.Agere Systems (Lucent Microelectronics) - San Jose, CASMTS Analog Design Engineer - Optical Access & Transport Group• Designed a 10GHz TxPLL (specifically the Charge Pump and LC-Tank VCO cells) for the OC-192 Transceiver. The measured Peak-to-Peak Jitter is < 6ps (or 60mUI).• Designed a 622MHz JaPLL for the OC-192 Transceiver. This circuit is used in conjunction with an external VCXO for reference clock jitter cleanup (or attenuation). Measurements show that this circuit is fully functional.• Designed a 622MHz Reference Clock Multiplexer for the OC-192 Transceiver. This circuit is used to route the reference clocks to the appropriate destination for each configured clock mode.• Modified/Optimized the pre-existing 16:1 TxMUX design (specifically the MUX Core and Bias cells) for the OC-192 Transceiver. This was needed to eliminate a clock divider oscillation and timing issues.• Designed a matrix of 5 10GHz TxPLLs for a test chip to investigate the feasibility of building low jitter, SONET compliant clock generation PLLs in 0.13um CMOS. Each of the 5 TxPLLs had a different LC or Varactor combination. The test chip was successful and enabled the OC-192 Optical Transceiver project to continue.Lucent Microelectronics - San Jose, CAMTS Analog Design Engineer - Netcom Group• Modified/Optimized a pre-existing 0.16um CMOS 250MHz 7-Bit Flash ADC with 4:1 Interpolation design for a 1G Ethernet project (which was subsequently cancelled).

Responsibilities included the design and evaluation of circuits which contain the analog and mixed-signal cells necessary to support CPE’s embedded processor designs. The simulation tools were primarily Cadence’s Framework suite of programs such as Analog Artist, Spectre HDL, Verilog XL, etc.Completed projects included:• Designed a Gating Timing Clock Recovery Circuit which extracts a 1.5GHz Clock from a serial 1.5Gb/s Data Stream. The design was in a 0.18um CMOS process (for a Serial ATA project).• Designed the Core PLL blocks: Phase Comparator, Charge Pump, Loop Filter, VCO (Voltage Controlled Oscillator), for a 1.5GHz Clock Synthesizer in the 0.18um CMOS process (for the Serial ATA project).• Designed a Differential Receiver with a bandwidth of 4GHz in the 0.18um CMOS process (for the Serial ATA project).• Designed a Programmable PLL Lead-Lag Filter using the Miller Capacitance amplification technique in the 0.18um CMOS process.• Designed the Core PLL blocks (except the VCO) for a 500MHz, 15ps 1-Sigma jitter Clock Synthesizer in the 0.18um CMOS process.• Designed an LVDS (Low Voltage Differential Signaling) Transceiver with 3 Levels of Programmable Drive Current in a 0.35um CMOS process.• Designed a PLL VCO block for a 400MHz, 15ps 1-Sigma jitter Clock Synthesizer in the 0.35um CMOS process (for a IEEE1394a project).• Designed a BandGap Voltage Reference with a 5% voltage deviation across temperature, process, & supply (for the IEEE1394a project).• Designed an Operational Amplifier with 62dB of Open Loop Gain, 60MHz of unity gain bandwidth, 60mA of available output current, and unity gain stability (for the IEEE1394a project).

Responsibilities included... Learning, analyzing, utilizing, then deploying state-of-the-art test development tools among National’s product groups. Virtual Test (ie. Tester/Loadboard/DUT simulation) is a major area of focus for highly integrated mixed-signal devices.... Loadboard hardware design and corresponding software generation (for the MegaTest Voyager / MCT3120 ATE platform) to fully test & characterize high performance Hard Disk Drive Magnetic Recording Peak-Detect and PRML Read Channel devices.Completed projects included:• Successfully demonstrated the Cadence/IMS Dantes Virtual Test environment using a hierarchical Verilog/Spectre model of National’s LMB4015 Vacuum Florescent Display Driver with the HDL/AHDL models of the Teradyne A580 ATE platform.• Provided the entire ATE solution for National’s LMB4015 Vacuum Florescent Display Driver. This entailed writing the Verilog testfixture scripts to generate the test patterns, running the simulations in the VERILOG-XL environment, cycle-izing the patterns for the ATE using the TSSI tool, writing the program code, and finally debug and delivery.

Responsibilities included program development for PC-based LCD VGA graphics integrated circuits and a tester-to-tester program transfer.Completed projects included:• The development of the test program for the GD6416 LCD VGA custom graphics chip on the MegaTest MegaOne tester. The vectors were generated using Cirrus' proprietary logic simulation tools.• Transfer of the existing test program for the GD6420 LCD VGA graphics chip from the MegaTest MegaOne tester to the Credence Vista Vision 2001 tester.

Duties included the responsibility for two new mass storage devices: the DP8467 & DP8491 Magnetic Disk Drive Data Path Electronics chips. Responsibilities included: 1) generation of IEEE-488 based automated lab parameter extraction / characterization system; 2) analysis & optimization of production test methodologies; 3) analysis of design modifications & their effectiveness.Completed projects included:• Designed an automated bench test system using an HP9836, Tek DSA 601 Oscilloscope, and other equipment to test Pulse Detector/ Synchronizer/ Synthesizer circuits of DP8491. Tests include AGC operation, Pulse Pairing & Window Truncation.• Designed an automated bench test to measure the Pulse Pairing parameter for the DP8464 Pulse Detector over a wide frequency range.• Wrote a utility program to store/retrieve configuration of a RS-680 Word Generator onto/from a floppy diskette.

Duties included the design and implementation of an IEEE-488 based system used to test and characterize wafers and packaged linear circuits, and to extract SPICE parameters for the improvement of the BJT and Diode models. Also analyzed device & wafer level failures & correlated activities between Linear LSI, Component, and Systems Engineering, Production Test, and Vendors.Completed projects included:• Designed IEEE-488 based system & wrote the required drivers & test routines for the testing & characterization of the 3682 Disk Drive R/W Amplifier & other Read Channel devices (e.g. Channel Amplifier, Peak Detector, Pulse Generator).• Participated in resolving a major zener diode failure mechanism detected in certain vendor fabricated wafer lots.• Interfaced some PC-AT based SPICE Pre/Post Processing Software with an Amdahl V8 mainframe which ran SPICE 2G.6.• Wrote an HP Plotter driver routine using input from an HP 8505A Network Analyzer.