DFT integration/validation• Implemented and validated HVM reset both pre and post Silicon on several projectso Modified the functional reset for use on both wafer (sort) and package (class) testers using only the tap.o Added debug/tracking featureso Wrote scripts to override fuses via the tapo Validated the design pre-silicon in simulationo Scripted the generation of all HVM reset headerso Led the power-on team in post-silicon for HVM reseto Worked closely with the manufacturing team in Malaysia throughout the design cycle to meet the needs of all DFT content• Integrated and validated boundary-scan pre-silicon using Tessent• Validated scan networks, pre-silicon in simulation• Developed and scripted collateral for the tap networkVector based equivalence• Validated equivalence between schematic and RTL using a vector-based equivalence tool and simulation on several projects• Technical lead of a team of 8 engineers