Digital Design Sr Manager
Current
Apr 2021 - Present
AeroLeads people directory · profile
Alberto Furlan Email & Phone Number
Digital Design Sr Manager presso TDK InvenSense
at
TDK InvenSense
1 work email found
@invensense.com
LinkedIn matched
✓ Verified May 2026
4 data sources
Profile completeness 100%
Current company
Role
Digital Design Sr Manager presso TDK InvenSense
Location
Milan, Lombardy, Italy
Company size
Who is Alberto Furlan? Overview
A concise factual answer block for searchers comparing this professional profile.
Quick answer
Alberto Furlan is listed as Digital Design Sr Manager presso TDK InvenSense at TDK InvenSense, a company with 710 employees, based in Milan, Lombardy, Italy. AeroLeads shows a work email signal at invensense.com and a matched LinkedIn profile for Alberto Furlan.
Alberto Furlan previously worked as Digital Design Sr Manager at Tdk Invensense and Digital Design Manager at Tdk Invensense. Alberto Furlan holds Electronic Engineer, Electronics And Automation from Politecnico Di Milano.
Company email context
Email format at TDK InvenSense
This section adds company-level context without repeating Alberto Furlan's masked contact details.
{first_initial}{last}@invensense.com
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AeroLeads found 1 current-domain work email signal for Alberto Furlan. Compare company email patterns before reaching out.
Profile bio
About Alberto Furlan
Alberto Furlan is a Digital Design Sr Manager presso TDK InvenSense at TDK InvenSense. He possess expertise in rtl design, soc, integrated circuit design, logic synthesis, asic and 14 more skills.
Listed skills include Rtl Design, Soc, Integrated Circuit Design, Logic Synthesis, and 15 others.
Current workplace
Alberto Furlan's current company
Company context helps verify the profile and gives searchers a useful next step.
Tdk Invensense
7 roles
Alberto Furlan work experience
A career timeline built from the work history available for this profile.
Digital Design Manager
Nov 2019 - Mar 2021
Digital Design Engineer – Principal
May 2019 - Oct 2019
Jul 2010 - May 2019
Digital Design Manager
Digital design group management for Data Storage products development.
Oct 2007 - Jun 2010
Project Leader
Design Project Leader for Data Storage products.Supervise all the steps of the project, from specification definition to signoff.
May 2006 - Oct 2007
Digital Designer
Specification definition, high speed rtl design, RTL to gate synthesis, functional verification, DFT structures responsible and ATPG patterns generation, ATE and reliability test responsible, laboratory silicon validation.
May 2000 - May 2006
Team & coworkers
Colleagues at TDK InvenSense
Other employees you can reach at invensense.com. View company contacts for 710 employees →
PB
Philippe Ballard
Colleague at Tdk Invensense
Grenoble, Auvergne-Rhône-Alpes, France, France
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NL
Nancy Liu
Colleague at Tdk Invensense
Sunnyvale, California, United States, United States
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RW
Raymond Wong
Colleague at Tdk Invensense
San Jose, California, United States, United States
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BU
Burhan Udin
Colleague at Tdk Invensense
Regol, West Java, Indonesia, Indonesia
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VP
Vincent Pham
Colleague at Tdk Invensense
San Jose, California, United States, United States
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NT
Narendra Tiwari
Colleague at Tdk Invensense
Noida, Uttar Pradesh, India, India
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KO
Katarina Orosova Dobrovodska
Colleague at Tdk Invensense
Slovakia, Slovakia
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AB
Alice Baluni
Colleague at Tdk Invensense
Saratoga, California, United States, United States
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PM
Philippe Maneta
Colleague at Tdk Invensense
Greater Grenoble Metropolitan Area, France
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JW
Justin Wu
Colleague at Tdk Invensense
Hsinchu City, Taiwan, Taiwan, Taiwan, Province Of China
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Philippe Ballard
Colleague at Tdk Invensense
Grenoble, Auvergne-Rhône-Alpes, France, France
View →
NL
Nancy Liu
Colleague at Tdk Invensense
Sunnyvale, California, United States, United States
View →
RW
Raymond Wong
Colleague at Tdk Invensense
San Jose, California, United States, United States
View →
BU
Burhan Udin
Colleague at Tdk Invensense
Regol, West Java, Indonesia, Indonesia
View →
VP
Vincent Pham
Colleague at Tdk Invensense
San Jose, California, United States, United States
View →
NT
Narendra Tiwari
Colleague at Tdk Invensense
Noida, Uttar Pradesh, India, India
View →
KO
Katarina Orosova Dobrovodska
Colleague at Tdk Invensense
Slovakia, Slovakia
View →
AB
Alice Baluni
Colleague at Tdk Invensense
Saratoga, California, United States, United States
View →
PM
Philippe Maneta
Colleague at Tdk Invensense
Greater Grenoble Metropolitan Area, France
View →
JW
Justin Wu
Colleague at Tdk Invensense
Hsinchu City, Taiwan, Taiwan, Taiwan, Province Of China
View →
2 education records
Alberto Furlan education
Electronic Engineer, Electronics And Automation
Certificate In Electronics, Electronics
Itis Parco Nord
FAQ
Frequently asked questions about Alberto Furlan
Quick answers generated from the profile data available on this page.
What company does Alberto Furlan work for?
Alberto Furlan works for TDK InvenSense.
What is Alberto Furlan's role at TDK InvenSense?
Alberto Furlan is listed as Digital Design Sr Manager presso TDK InvenSense at TDK InvenSense.
What is Alberto Furlan's email address?
AeroLeads has found 1 work email signal at @invensense.com for Alberto Furlan at TDK InvenSense.
Where is Alberto Furlan based?
Alberto Furlan is based in Milan, Lombardy, Italy while working with TDK InvenSense.
What companies has Alberto Furlan worked for?
Alberto Furlan has worked for Tdk Invensense and Stmicroelectronics.
Who are Alberto Furlan's colleagues at TDK InvenSense?
Alberto Furlan's colleagues at TDK InvenSense include Philippe Ballard, Nancy Liu, Raymond Wong, Burhan Udin, and Vincent Pham.
How can I contact Alberto Furlan?
You can use AeroLeads to view verified contact signals for Alberto Furlan at TDK InvenSense, including work email, phone, and LinkedIn data when available.
What schools did Alberto Furlan attend?
Alberto Furlan holds Electronic Engineer, Electronics And Automation from Politecnico Di Milano.
What skills is Alberto Furlan known for?
Alberto Furlan is listed with skills including Rtl Design, Soc, Integrated Circuit Design, Logic Synthesis, Asic, Dft, Verilog, and Ic.
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