Author of best-selling Industry Text "Design for Test for Digital ICs and Embedded-Core Systems"Author of more than 50 papers, publications, and eBooks in the field of DFT, Test Automation, Test and Test/Debug Security; Inventor on more than 20 issued patents and defensive pubs in the field of Test, Test Automation, Design-for-Test/Debug, and Test/Debug Security.Vice-Chair of the IEEE 1687-2014 Standardization Group and driver/member of the Working Group team that developed the 1687 IJTAG Hardware Architecture Specification and normative rules for embedded instruments and connectivity networks. Still actively marketing the standard and driving adoption. Co-Chair of the iNEMI Phase 2/Phase 3 BIST projects whose goal was to identify how best to use or reuse test features embedded within chips to facilitate modern non-intrusive (NBT) board test, and to recommend or generate a standardization effort.Main contact for IEEE study groups involving 1687.1 (Alternate controllers for 1687 embedded instrument access networks, e.g. SPI or I2C), and 1687.S (test access security associated with embedded on-chip content and the extension of including the secure chip onto the board in such a way to meet board security goals).Currently investigating developing products based on the concepts of the IEEE 1687, as well as IEEE 1500 and IEEE 1149.7.Senior Member of the IEEE.Specialties: Customer interaction, Technical Marketing, Innovation (inventions and patents), Publication and Presentation, Teaching and Training, Design and Test Flow Methodology Development, IP Development, Software Tool Creation, Design-for-Test, Design-for-Debug&Diagnosis, Design-for-Yield, Design-for-Power-Analysis, AC Scan, Test Data Collection and Analysis, Structural Tester Architecture Development, and Test and Debug Access Security.IEEE Standards: 1450 STIL; 1149 JTAG; 1500 Core Test; 1687 IJTAG; 1149.7 Compact JTAG
Listed skills include Dft, Semiconductors, Debugging, Ic, and 46 others.