Alfred Crouch Email and Phone Number
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Author of best-selling Industry Text "Design for Test for Digital ICs and Embedded-Core Systems"Author of more than 50 papers, publications, and eBooks in the field of DFT, Test Automation, Test and Test/Debug Security; Inventor on more than 20 issued patents and defensive pubs in the field of Test, Test Automation, Design-for-Test/Debug, and Test/Debug Security.Vice-Chair of the IEEE 1687-2014 Standardization Group and driver/member of the Working Group team that developed the 1687 IJTAG Hardware Architecture Specification and normative rules for embedded instruments and connectivity networks. Still actively marketing the standard and driving adoption. Co-Chair of the iNEMI Phase 2/Phase 3 BIST projects whose goal was to identify how best to use or reuse test features embedded within chips to facilitate modern non-intrusive (NBT) board test, and to recommend or generate a standardization effort.Main contact for IEEE study groups involving 1687.1 (Alternate controllers for 1687 embedded instrument access networks, e.g. SPI or I2C), and 1687.S (test access security associated with embedded on-chip content and the extension of including the secure chip onto the board in such a way to meet board security goals).Currently investigating developing products based on the concepts of the IEEE 1687, as well as IEEE 1500 and IEEE 1149.7.Senior Member of the IEEE.Specialties: Customer interaction, Technical Marketing, Innovation (inventions and patents), Publication and Presentation, Teaching and Training, Design and Test Flow Methodology Development, IP Development, Software Tool Creation, Design-for-Test, Design-for-Debug&Diagnosis, Design-for-Yield, Design-for-Power-Analysis, AC Scan, Test Data Collection and Analysis, Structural Tester Architecture Development, and Test and Debug Access Security.IEEE Standards: 1450 STIL; 1149 JTAG; 1500 Core Test; 1687 IJTAG; 1149.7 Compact JTAG
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Chief Scientist & Director Of Hardware EngineeringAmida Technology Solutions May 2017 - PresentWashington, District Of Columbia, UsAs Director of HW Engineering, I am responsible for developing Cybersecurity and Hardware Assurance solutions that involve creating hardware; or are solutions (that may include both Software and Hardware) that can be applied to hardware. For example, hardware cybersecurity threats are either built-in threats such as Trojans, Back-Doors or Counterfeits (IP, ICs, boards); or external threats such as Tampering or Virus attacks. The solutions being investigated and developed can apply to today's critical systems -- medical, automotive, government/military -- and will extend to the more general purpose such as the Industrial Internet of Things (IIoT) and the Internet of Things (IoT).
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Adjunct ProfessorSouthern Methodist University Jan 2017 - May 2017Dallas, Tx, UsDeveloping and Teaching a graduate level class on Hardware Security and Trojan Detection (CSE 7369-795)for the Computer Science and Engineering Department, Lyle School of Engineering -
Chief TechnologistSiliconaid Solutions, Inc Jul 2015 - Feb 2017Austin, UsAs Chief Technologist it is my goal to work with customers, partners, the development team and the senior management team to help set product and methodology directions based around the IEEE Test Standards -- IEEE 1149.1, 1149.6, 1500, 1687. This involves creating opportunities, tool features, methodologies, and strategies for the application and use of SiliconAid's JTAG and IJTAG software products. I will also continue to be involved with the IEEE Standards to pursue the P1687.1 Alternate Controllers (e.g. connecting I2C, SPI, SWD, etc. to embedded 1687 access networks) and Test-Debug Security (e.g. locking, blocking and hiding embedded instruments and registers, and obfuscating, encrypting embedded instrument data). -
Chief Technologist & Director Of Ijtag R&DAsset-Intertech Mar 2008 - May 2015Plano, Texas, UsAs Chief Technologist and Director of IJTAG R&D, and having been the Vice-Chair of the IEEE P1687 Working Group, I worked with customers and partners to develop three new product directions based on the concepts based around the IJTAG Standards. This involved creating tools and methodologies to access test, debug, monitoring, and configuration instruments embedded within IC's and largely based on using the 1149.1 Test Access Port or an Embedded CPU to access, control, configure, operate, and collect data from these instruments. The product directions created involved an IJTAG End-User tool to use BSDL, ICL and PDL to identify, manage and operate embedded instruments; an FPGA-Controlled Test tool to turn on-board FPGA's into embedded testers by generating an access network with targeted embedded instruments to be used as a temporary board/system tester; and a test-debug security methodology based on an ASSET issued patent of being able to segment and lock scan paths within an IJTAG network. -
Chief Scientist And Director Of Dft R&DVerigy Jan 2008 - Mar 2008Tokyo, JpVerigy acquired Inovys and my position changed to more of a Strategic Marketing Assessment instead of Technology Exploration and Development. -
Chief Scientist And Director Of Dft R&DInovys Corporation Oct 2001 - Dec 2007UsAs Chief Scientist, Director of R&D in the Austin Verigy DFx Technology Center, and the Director of EDA Partnerships, it was my job to work with customers and partners to develop new links and uses between structural testers and design-side tools such as ATPG, STA, Layout, and Debug and Diagnosis. In addition, to push the bounds of the structural tester with DFT techniques that enabled it to be used to characterize timing, power, thermal limits, and functional operation using AC Scan, BIST, and loadboard micro-instrumentation. And to have developed yield and failure-analysis solutions based on structural test techniques and data collection. -
Design-For-Test ManagerMotorola Jan 1992 - Oct 2001Chicago, Illinois, UsIn my last position, I developed DFT methodologies and managed a DFT team involved with DFT architecture development and vector generation for various microprocessor chips and cores -- such as the 68k/ColdFire. Prior to that I was the DFT Architect for the 68060 and ColdFire microprocessors. I received the Distinguished Innovator award for receiving more than 10 issued patents. -
Design-For-Test EngineerDigital Equipment Corp. Jan 1990 - Jan 1992Houston, Texas, UsDeveloped Test Methodology and Automation Solutions for ASICs being designed in-house and to be manufactured by several different ASIC Manufacturers (LSI, VLSI, Motorola, TI, etc.) -
Design-For-Test EngineerTexas Instruments 1987 - 1990Dallas, Tx, UsImplemented test and testability solutions, and linked these to test automation for the DSEG (Defense Electronics) Group. Worked on many systems such as thermal imagers, board-based and embedded computers, GPS locators, and sophisticated built-in diagnostic systems. Also worked on the precursor applications to the IEEE 1149.1 JTAG standard (ratified in 1991).
Alfred Crouch Skills
Alfred Crouch Education Details
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University Of KentuckyElectrical Engineering: Quantum Electronics -
University Of KentuckyElectrical Engineering
Frequently Asked Questions about Alfred Crouch
What company does Alfred Crouch work for?
Alfred Crouch works for Amida Technology Solutions
What is Alfred Crouch's role at the current company?
Alfred Crouch's current role is Director of Hardware Engineering at Amida Technology Solutions.
What is Alfred Crouch's email address?
Alfred Crouch's email address is ac****@****ech.com
What is Alfred Crouch's direct phone number?
Alfred Crouch's direct phone number is +120273*****
What schools did Alfred Crouch attend?
Alfred Crouch attended University Of Kentucky, University Of Kentucky.
What skills is Alfred Crouch known for?
Alfred Crouch has skills like Dft, Semiconductors, Debugging, Ic, Eda, Embedded Systems, Testing, Asic, Jtag, Soc, Hardware Architecture, Processors.
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