Aleksandr Senchenko Email & Phone Number

Belgrade, Rs

Белград, Сербия

Worked on the HRP UWB PHY IP (IEEE 802.15.4).- Transmitter (TX): Updated microarchitecture and RTL to meet the latest standard requirements- Receiver (RX): Developed multiple signal processing blocks based on algorithms, including inflection points search, SFD pattern detection, and Viterbi decoding. Designed microarchitecture optimal for area and power efficiency, matching the processing latency constraints.- Created standalone verification environments for developed blocks, using given test vectors from the algorithm team. Developed Python models for easier debugging.Led a digital design internship program, guiding interns through designing the microarchitecture of a simplified MIPI DSI-TX from given requirements, RTL coding, developing a simple testbench as well as using an UVM environment, and running linting, CDC, and RDC checks.

Москва, Россия

• Developed RTL for DSI-2 TX controller and completed functional verification (using Cadence VIP), CDC analysis, logic synthesis, STA, FPGA prototyping, gate-level simulation• Integrated third-party IP-Cores• Took part in AXI4-based SoC architecture planning, developed its system-level RTL, wrote test plan and provided support at all stages to tapeout• Performed FPGA prototyping of SoC and IP-Cores

Москва, Россия

Developed RTL and unit-tests for following blocks • On-Chip temperature sensor controller• OTP memory controller • JTAG-based configuration block

Магистр, Вычислительно-Измерительные Системы

Master'S Degree

Took part in double master programm between Moscow Power Engineering Institute (Moscow, Russia) and TU Ilmenau (Germany)

Бакалавр, Вычислительно-Измерительные Системы

Master'S Degree