As a highly motivated and results-driven individual, I hold a B.Tech. degree in Electronics and Communication Engineering, which provided a strong technical foundation for my career in VLSI Engineering. I further honed my expertise by undergoing L1 training in VLSI Designing at Eklakshya Innovation Labs in Hubli. This experience allowed me to deepen my understanding of VLSI design principles and exposed me to industry-standard tools and methodologies.For the past year, I have been working as a Project Associate at CDAC Bangalore, where I specialize in RTL (Register Transfer Level) design for FPGA implementations. In this role, I have gained significant experience in the FPGA design flow, including logic synthesis, timing analysis, and functional verification. I am proficient in using tools such as Xilinx Vivado, Questa Sim, and ModelSim, and I have a solid understanding of RTL coding using Verilog, testbench creation, and debugging.My strong foundation in digital logic design and hands-on experience with FPGA development has equipped me with the skills necessary to tackle complex design challenges and deliver efficient, high-performance solutions. I am well-versed in synthesis, floorplanning, and timing closure for FPGA designs, ensuring that projects meet stringent performance and area constraints. I am passionate about staying at the forefront of technological advancements in the VLSI domain and am eager to contribute to innovative projects that push the boundaries of what's possible in semiconductor design.