Alexandre Cano Email & Phone Number

- FPGA project management. - Technical lead for a team of four FPGA/HW designers. - Requirements analysis, specification, architecture, work planning. - FPGA/ASIC and FPGA SOC development. - Specification, design, coding, simulation (BFM), timings analysis on FPGA. - Design of electronic boards, schematic, placement and PCB routing supervisor. - Signal integrity - JTAG and tests definition.Computer languages: VHDL, Verilog, C, TCL.Target FPGA: XILINX, ALTERA, ACTEL.Processors-DSP: Cortex A9, A8, M0, AT91, PowerPC 440,405, Coldfire, TigerSharc.Network components: M88E6321, M88E6161, M88E1111, M88E1112, LAN91C111.Memories: SDRAM, DDR, DDR2, NAND, EMMC.Bus: PCI, AXI, PLB, OPB, SGMII, RGMII.Protocols: IEE802.3ab, IEE802.3z, IEEE.1588-V2, JESD84-A44, UDP, TCP/IP, HDLC.Tools: Vivado, Quartus, Libero, Modelsim, Synplify, Cadstar, PCB Browser, Hyperlink, Temento.

Listed skills include Fpga, Xilinx, Altera, Vhdl, and 2 others.