Alexandre Charvier Email & Phone Number

Gières, Fr

Grenoble, Auvergne-Rhône-Alpes, France

Product Management (ASIC and AI Processing IPs)- Manage Artificial Intelligence (AI) products from roadmap definition & feasibility study to customer delivery. Contract filling, budgetary quotation, program management, …- Products/demochips (HW + SW): MCU (ARM or RISCV cores), DSP (16 x RISCV CV32E40P cores), NPU, Cache controller, RTC, verification of CV32E40P v2 core for OpenHWGroup- ASIC: Defense, Aero, Consumer. ST28FDSOI, GF22FDX, TSMC22ULL …- Ensure pre-sales, contract and post-delivery support for all technical topics working closely with BD, marketing, and sales teams to meet FY budget- Report KPIs to staff managementOperation Management- Manage operational execution following actual vs initial budget, milestones, and risks to ensure proper payment plan and/or deliveries- Define budget, workload plan for people allocation & arbitration, material & EDA needs. Up to 30+ people. HW (archi, design, verification), ME activities (synthesis, TA, DFT) and SW activities (SDK, VP, …)- Define project quotations and project planningsPeople Management- Drive and federate 30+ people (France + Singapore sites) including full remote workers- Responsible for hiring plan, interviews, annual evaluation & professional reviews- Skill plan & technical training plan definition- QWL, regular weeklies, knowledge sharing, webinars, and conferences- Team of 10+ people in 2017, 30+ in 2022Technical Leader- Responsible for FE and ME methodology development. Strong involvement in sharing and unifying methodologies/ flows- Huge hands-on digital design & verification experience + SoC architecture- Defined, created, and trained >40p to FE methodology.- Technical leader of 340mm² video processing ASIC (GF22FDX) Misc- Strongly involved in Singapore’s site creation and ramp-up- Strong involvement in transversal topics, reference manager for HR activities- Created subcontractors’ management process from scratch- Experience with ISO26262 standard at IP level

Meylan, Rhône-Alpes, France

Grenoble Area, France

Verification technical leader- In charge of all verification activities including IP/SOC verification, methodologies, reporting, continuous improvments, EDA licences management- Create the verification activity from scratch including verification flow, testbench infrastructure, reporting, CI (Jenkins)Low power technical leader- In charge of technical activity related to LP methodologies with UPF- SoC architecture- In charge of Qingshan demochip SoC architecture- Functional specification and power intent specificationPeople Management- Manage 4 people including annual evaluation, skills development plan...

Grenoble Area, France

SoC verification/design for Set-Top-Box STiH412, STiH312, STiH337 product family.Verification activities- Verification technical lead for STiH337 product- Test plan definition and implementation for many subsystems : GPU, graphic blitter, JPEG decoder, HDMI, Boot devices- Low-power verification (UPF-based) definition, platform updates and executionDesign activities- GPU, graphic blitter integration at SoC level- Boot devices (NAND, SPI, eMMC) sub-systems integration at SoC level- RTL design for SoC infrastructurePower estimation activities- Create, develop and execute SoC infrastructure power estimation flow- Work closely with system architecture and implementation team- Extract power consumption, clock gating efficiency, power density for SoC IPs- SQL database for power figures managementInfrastructure :- Tests development in C- Tests database management with GIT/Repo- Continuous integration using Jenkins- SoC SQL database development using Java

Grenoble Area, France

Leading activities- Verification plan definition and execution with respect to SoC requirements for ST-Ericsson U85xx, U86xx, U96xx product families- Relationship with Imagination Technologies- Relationship with ST-Ericsson SoC teamMain activities- Integration of "Imagination (IMG)" IP (SGX544, Rogue) into ST-Ericsson GPU sub-sytem- Dedicated power management structure around IMG Rogue IP- RTL verification- GPU system C modeling for SoC teamPerformances characterization- Benchmarking- Memory latencies and core frequency variationLow Power (LP) verification- Dedicated verification plan- Advanced LP technics, multi-voltage verification- FDSOI technologyPower estimation- Same benchmarks as for performances characterization- Extract leakage and dynamic power consumption- Temperature and voltage scaling- Clock gating efficiency- Bulk and FDSOI librariesVerification methodologies / platform- SystemC/TLM based platform based- C-langage verification SW- Synopsys simulator for RTL and LP verification- Certitude- SQL database for verification results management (non regression status, coverage metrics, performances...)

Grenoble Area, France

- H264 / MP4 / VC1 video encoder/decoder environment - VC1 codec sub-system verification - Power estimation methodology, simulations and reporting for all codecs - XTREME cadence co-emulation methodology - GATE level zero/back-annotated simulations before PG

Grenoble Area, France

Video encoder/decoder IP verification- Variable-length-decoder block level verification- Build verification plan, platform & test implementation- Review with architects & designers- e/Specman verification environment- C language verification SW- Scripting

Grenoble Area, France

Subcontractor in ST-Microelectronics as SoC verification engineer on Nomadik project

Master Of Science (Msc), Microelectronics & Telecommunications

Activities and Societies: PSI Electronics, ST Microelectronics

Bachelor Of Science (Bsc), Electrical, Electronics And Communications Engineering