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Avinash Lingamneni Email & Phone Number
ML Hardware Architect
at
Google
2 work emails found
@google.com
1 phone found area 713
LinkedIn matched
4 data sources
Profile completeness 100%
Current company
Role
ML Hardware Architect
Location
San Jose, California, United States
Company size
Who is Avinash Lingamneni? Overview
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Quick answer
Avinash Lingamneni is listed as ML Hardware Architect at Google, a company with 315106 employees, based in San Jose, California, United States. AeroLeads shows a work email signal at google.com, phone signal with area code 713, and a matched LinkedIn profile for Avinash Lingamneni.
Avinash Lingamneni previously worked as Architecture and Design Engineer for TPUs at Google and Principal Design Engineer at Cadence Design Systems. Avinash Lingamneni holds Doctor Of Philosophy (Ph.D.), Electrical And Computer Engineering from Rice University.
Company email context
Email format at Google
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{first_initial}{last}@google.com
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Profile bio
About Avinash Lingamneni
I am currently working on the architecture and design of machine learning accelerators (TPUs) at Google.Previously, I was a Principal Design Engineer in Tensilica R&D at Cadence Design Systems where I led the DSP engineering efforts on processors targeted for Computer Vision (deep learning), Audio/Voice/Speech and IoT applications. I received my Ph.D. in Electrical and Computer Engineering (ECE) from Rice University. My Ph.D. research was in the domain of inexact/approximate computing with over 25 refereed publications, 1 patent and a best paper award.
Listed skills include Vlsi, Algorithms, Digital Signal Processors, Matlab, and 45 others.
Current workplace
Avinash Lingamneni's current company
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Google
8 roles
Avinash Lingamneni work experience
A career timeline built from the work history available for this profile.
Architecture And Design Engineer For Tpus
CurrentWorking on architecture and design of cloud TPUs for accelerated machine learning.
Nov 2017 - Present
Principal Design Engineer
DSP Engineering lead and ISA architect for new Tensilica DSPs with responsibilities ranging from ISA definition, microarchitecture prototyping & optimization and documentation to coordinating project deliverables across the application software, implementation, verification and CAD teams. DSP designs include: (a) Tensilica® HiFi 3z DSP for.
Jun 2016 - Nov 2017
Lead Design Engineer
i. Led the design, implementation and optimization of the micro-architecture for the new Tensilica® Fusion DSP core with ISA for Audio/Voice/Speech, wireless communications and floating point, targeted for Internet-of-Things (IoT) and wearables applications. Also, engaged in ISA feedback, verification, documentation and PPA characterizations. ii. Designed.
May 2014 - Jun 2016
Doctoral Student In Electrical And Computer Engineering
i. Conceptualized, modeled, implemented and validated several inexact/approximate computing based design approaches to realize ultra energy-efficient circuits in applications including DSP (FFTs, Filters), multimedia (JPEG, H.264 codecs), wireless communications (OFDM transceiver), neural network accelerators and atmospheric modeling simulators.ii..
Aug 2008 - Apr 2014
Phd Student Intern
i. Fabricated (all of design and validation) pipelined inexact Fast-Fourier Transform (FFT) accelerators in 65nm process achieving upto 75% datapath energy reduction for less than 1dB SNR loss.ii. Formulated algorithmic cross-layer co-design methodologies for design and optimization of inexact systems.
Jan 2011 - Dec 2012
Phd Student Intern
i. Fabricated (all of design and validation) of 64-bit inexact arithmetic circuits in 180nm (low power) achieving 2X-4.8X energy gains for tolerable quality degradation. ii. Developed a design automation framework for faster design and exploration of inexact digital circuits.
Jan 2010 - Jul 2010
Visiting Research Assistant
i. Worked on novel techniques to design and analyze approximate/inexact circuits at the Institute for Sustainable Nanoelectronics (ISNE) with Prof. Vincent Mooneyii. Developed the initial I-Slate architecture specifications and explored design possibilities.iii. Worked on building a CAD framework for designing inexact circuits including an in-house circuit.
May 2009 - Aug 2009
3 education records
Avinash Lingamneni education
Doctor Of Philosophy (Ph.D.), Electrical And Computer Engineering
Rice University
Master Of Science, Electrical & Computer Engineering
Rice University
Bachelor Of Technology (Hons.), Electronics And Communication Engineering With Honors In Vlsi & Embedded Systems
International Institute Of Information Technology Hyderabad (Iiith)
FAQ
Frequently asked questions about Avinash Lingamneni
Quick answers generated from the profile data available on this page.
What company does Avinash Lingamneni work for?
Avinash Lingamneni works for Google.
What is Avinash Lingamneni's role at Google?
Avinash Lingamneni is listed as ML Hardware Architect at Google.
What is Avinash Lingamneni's email address?
AeroLeads has found 2 work email signals at @google.com for Avinash Lingamneni at Google.
What is Avinash Lingamneni's phone number?
AeroLeads has found 1 phone signal(s) with area code 713 for Avinash Lingamneni at Google.
Where is Avinash Lingamneni based?
Avinash Lingamneni is based in San Jose, California, United States while working with Google.
What companies has Avinash Lingamneni worked for?
Avinash Lingamneni has worked for Google, Cadence Design Systems, Rice University, Csem, and Nanyang Technological University.
How can I contact Avinash Lingamneni?
You can use AeroLeads to view verified contact signals for Avinash Lingamneni at Google, including work email, phone, and LinkedIn data when available.
What schools did Avinash Lingamneni attend?
Avinash Lingamneni holds Doctor Of Philosophy (Ph.D.), Electrical And Computer Engineering from Rice University.
What skills is Avinash Lingamneni known for?
Avinash Lingamneni is listed with skills including Vlsi, Algorithms, Digital Signal Processors, Matlab, Simulations, Verilog, Modelsim, and Circuit Design.
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